Patents by Inventor Naoki Shouno

Naoki Shouno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5901080
    Abstract: A nonvolatile semiconductor memory device for storing data by introducing electrons into a floating gate through a tunneling oxide film under an electric field of a control gate includes a switching circuit for supplying a reference high voltage during a normal erase mode and a test bias voltage during a test mode. In the test mode, the switching circuit can create a status where a self-field is applied between the floating gate and the source, and makes it easy to find out cells that are deteriorated due to trapping of holes into the oxide film.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: May 4, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Shouno
  • Patent number: 5321296
    Abstract: There is disclosed a semiconductor device which has a first insulating film formed on a surface of a semiconductor substrate, a polysilicon layer formed on the first insulating film, a second insulating film formed on the polysilicon layer, and a metallic interconnection layer formed on the second insulating film. The polysilicon layer is formed thicker at a connection portion than other portions and is connected to the metallic interconnection layer via a hole formed in the second insulating layer. The film thickness of the polysilicon layer is large at the contact forming portion so that it is possible to prevent the contact hole from being formed passing through the polysilicon layer even if the lower polysilicon layer is excessively etched during the contact hole forming process.
    Type: Grant
    Filed: December 9, 1991
    Date of Patent: June 14, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Shouno