Patents by Inventor Naoki Tamaoki
Naoki Tamaoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10460050Abstract: A topography simulation apparatus includes a processor and a memory connected to the processor. The memory stores instructions executable by the processor to set a function indicating a position relationship between a point in a calculation region and a material surface in the calculation region. The memory stores further instructions executable by the processor to determine whether or not a particle moving in the calculation region collides with the material surface, and update a value of the function, responsive to determining that the particle collides with the material surface.Type: GrantFiled: September 1, 2016Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naoki Tamaoki
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Patent number: 9996639Abstract: In one embodiment, a topography simulation apparatus includes a division module to divide a calculating area for calculating topography of a substance into cells and express the topography using filled cells and vacant cells, and a calculation module to calculate a filling rate for a target cell based on processing rates for its neighboring cells. The calculation module calculates, based on the processing rates for the neighboring cells, contributing rates of the neighboring cells contributing to the filling rate for the target cell. The calculation module calculates, based on the contributing rates of the neighboring cells, the filling rate for the target cell. One of the contributing rates of the neighboring cells of the target cell depends on whether another neighboring cell of the target cell is a first cell whose filling ratio belongs to first range or a second cell whose filling ratio belongs to second range.Type: GrantFiled: March 13, 2015Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naoki Tamaoki
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Publication number: 20170262556Abstract: A topography simulation apparatus includes a processor and a memory connected to the processor. The memory stores instructions executable by the processor to set a function indicating a position relationship between a point in a calculation region and a material surface in the calculation region. The memory stores further instructions executable by the processor to determine whether or not a particle moving in the calculation region collides with the material surface, and update a value of the function, responsive to determining that the particle collides with the material surface.Type: ApplicationFiled: September 1, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naoki TAMAOKI
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Publication number: 20160380189Abstract: According to one embodiment, a manufacturing method of a magnetoresistive effect element includes forming a laminated structure on a substrate, the laminated structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having an invariable magnetization direction, and a non-magnetic layer between the first and second magnetic layers, forming a first mask layer having a predetermined plane shape on the laminated structure, and processing the laminated structure based on the first mask layer by using an ion beam whose solid angle in a center of the substrate is 10° or more.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi Ohsawa, Junichi Ito, Saori Kashiwada, Chikayoshi Kamata, Naoki Tamaoki
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Publication number: 20160070823Abstract: In one embodiment, a topography simulation apparatus includes a division module to divide a calculating area for calculating topography of a substance into cells and express the topography using filled cells and vacant cells, and a calculation module to calculate a filling rate for a target cell based on processing rates for its neighboring cells. The calculation module calculates, based on the processing rates for the neighboring cells, contributing rates of the neighboring cells contributing to the filling rate for the target cell. The calculation module calculates, based on the contributing rates of the neighboring cells, the filling rate for the target cell. One of the contributing rates of the neighboring cells of the target cell depends on whether another neighboring cell of the target cell is a first cell whose filling ratio belongs to first range or a second cell whose filling ratio belongs to second range.Type: ApplicationFiled: March 13, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naoki TAMAOKI
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Publication number: 20150205890Abstract: In one embodiment, a topography simulation apparatus includes a division module to divide a surface of a substance into a plurality of computing elements. The apparatus includes a first calculation module to calculate a surface movement rate in each computing element and to derive, for the plurality of computing elements, a first maximum which is a maximum of an absolute value of the surface movement rate. The apparatus includes a second calculation module to calculate a difference between surface movement rates in mutually adjacent computing elements and to derive, for the mutually adjacent computing elements among the plurality of computing elements, a second maximum which is a maximum of an absolute value of the difference between the surface movement rates. The apparatus includes a determination module to determine a time step for calculating a change in topography of the substance, based on the first or second maximum.Type: ApplicationFiled: April 28, 2014Publication date: July 23, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoki TAMAOKI, Yoshinori YOKOTA
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Patent number: 8821684Abstract: A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.Type: GrantFiled: January 30, 2009Date of Patent: September 2, 2014Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron LimitedInventors: Akio Ui, Naoki Tamaoki, Takashi Ichikawa, Hisataka Hayashi, Takeshi Kaminatsui, Shinji Himori, Norikazu Yamada, Takeshi Ohse, Jun Abe
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Publication number: 20140087483Abstract: According to one embodiment, a manufacturing method of a magnetoresistive effect element includes forming a laminated structure on a substrate, the laminated structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having an invariable magnetization direction, and a non-magnetic layer between the first and second magnetic layers, forming a first mask layer having a predetermined plane shape on the laminated structure, and processing the laminated structure based on the first mask layer by using an ion beam whose solid angle in a center of the substrate is 10° or more.Type: ApplicationFiled: March 19, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi OHSAWA, Junichi Ito, Saori Kashiwada, Chikayoshi Kamata, Naoki Tamaoki
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Patent number: 8548787Abstract: A calculating unit calculates either one of a reaction probability between a chemical species used in a semiconductor process and a semiconductor device and a deactivation probability of the chemical species, according to either one of a structure of the semiconductor device and a plurality of materials. A simulation unit performs a simulation of a physical phenomenon occurring in a reaction chamber based on either one of the reaction probability and the deactivation probability.Type: GrantFiled: November 6, 2006Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Naoki Tamaoki, Akio Ui, Toshiro Takase, Takashi Ichikawa
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Patent number: 8252193Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.Type: GrantFiled: March 20, 2008Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Akio Ui, Takashi Ichikawa, Naoki Tamaoki, Hisataka Hayashi, Akihiro Kojima
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Patent number: 8209155Abstract: A simulation method includes dividing a material surface into finite computational elements, and calculating a deposition rate or etching rate at each of the computational elements to simulate a feature profile of the material surface, the calculating including calculating an indirect effect of a first computational element on the deposition rate or etching rate of a second computational element. The calculating the indirect effect includes correcting a surface profile at the first computational element on the basis of a surface structure around the first computational element, and calculating the indirect effect on the basis of the corrected surface profile at the first computational element.Type: GrantFiled: August 15, 2008Date of Patent: June 26, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Ichikawa, Naoki Tamaoki, Toshiro Takase
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Patent number: 7942974Abstract: A method of cleaning a film-forming apparatus to remove a silicon-based material deposited on a constituent member of the film-forming apparatus after being used to form thin films includes introducing a first gas including fluorine gas and a second gas including carbon monoxide gas into the film-forming apparatus, and heating the constituent member. The constituent member includes quartz or silicon carbide and the silicon-based material includes silicon nitride, or the constituent member includes silicon carbide and the silicon-based material includes silicon oxide.Type: GrantFiled: September 26, 2005Date of Patent: May 17, 2011Assignees: Kabushiki Kaisha Toshiba, L'Air LiquideInventors: Naoki Tamaoki, Yuusuke Sato, Jun Sonobe, Takamitsu Shigemoto, Takako Kimura
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Publication number: 20090194508Abstract: A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Inventors: Akio UI, Naoki TAMAOKI, Takashi ICHIKAWA, Hisataka HAYASHI, Takeshi KAMINATSUI, Shinji HIMORI, Norikazu YAMADA, Takeshi OHSE, Jun ABE
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Publication number: 20090055143Abstract: A simulation method includes dividing a material surface into finite computational elements, and calculating a deposition rate or etching rate at each of the computational elements to simulate a feature profile of the material surface, the calculating including calculating an indirect effect of a first computational element on the deposition rate or etching rate of a second computational element. The calculating the indirect effect includes correcting a surface profile at the first computational element on the basis of a surface structure around the first computational element, and calculating the indirect effect on the basis of the corrected surface profile at the first computational element.Type: ApplicationFiled: August 15, 2008Publication date: February 26, 2009Inventors: Takashi Ichikawa, Naoki Tamaoki, Toshiro Takase
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Publication number: 20090048813Abstract: A simulation method is configured to simulate a feature profile of a material surface. The simulation method includes using an algorithm of repeating a step of calculating a surface growth rate and a step of skipping the calculation of the surface growth rate. The surface growth rate is calculated in the step of skipping the calculation of the algorithm if the material surface traverses a material interface.Type: ApplicationFiled: August 15, 2008Publication date: February 19, 2009Inventors: Takashi Ichikawa, Naoki Tamaoki, Toshiro Takase
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Publication number: 20080237185Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.Type: ApplicationFiled: March 20, 2008Publication date: October 2, 2008Inventors: Akio UI, Takashi Ichikawa, Naoki Tamaoki, Hisataka Hayashi, Akihiro Kojima
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Publication number: 20070134433Abstract: Silicon nitride film is formed on substrate (112) by feeding trisilylamine and ammonia into a CVD reaction chamber (11) that contains a substrate (112). The ammonia gas/trisilylamine gas flow rate ratio is set to a value of at least about 10 and/or the thermal CVD reaction is run at a temperature no greater than about 600° C. Silicon oxynitride is obtained by introducing an oxygen source gas into the CVD reaction chamber (11). This method avoids the production of ammonium chloride and/or the incorporation of carbonaceous contaminants which are detrimental to the quality of the deposited film.Type: ApplicationFiled: February 14, 2007Publication date: June 14, 2007Inventors: Christian DUSSARRAT, Jean-Marc Girard, Takako Kimura, Naoki Tamaoki, Yuusuke Sato
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Publication number: 20070118341Abstract: A calculating unit calculates either one of a reaction probability between a chemical species used in a semiconductor process and a semiconductor device and a deactivation probability of the chemical species, according to either one of a structure of the semiconductor device and a plurality of materials. A simulation unit performs a simulation of a physical phenomenon occurring in a reaction chamber based on either one of the reaction probability and the deactivation probability.Type: ApplicationFiled: November 6, 2006Publication date: May 24, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoki Tamaoki, Akio Ui, Toshiro Takase, Takashi Ichikawa
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Patent number: 7192626Abstract: Silicon nitride film is formed on substrate by feeding trisilylamine and ammonia into a CVD reaction chamber that contains a substrate. The ammonia gas/trisilylamine gas flow rate ratio is set to a value of at least about 10 and/or the thermal CVD reaction is run at a temperature no greater than about 600° C. Silicon oxynitride is obtained by introducing an oxygen source gas into the CVD reaction chamber. This method avoids the production of ammonium chloride and/or the incorporation of carbonaceous contaminants which are detrimental to the quality of the deposited film.Type: GrantFiled: September 24, 2003Date of Patent: March 20, 2007Assignee: L'Air Liquide, Société Anonyme á Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procédés Georges ClaudeInventors: Christian Dussarrat, Jean-Marc Girard, Takako Kimura, Naoki Tamaoki, Yuusuke Sato
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Publication number: 20060216875Abstract: A method for annealing a semiconductor substrate by light irradiation, includes depositing a translucent film with a predetermined thickness on a semiconductor substrate. The translucent film has a refractive index that is smaller than that of the semiconductor substrate. The thickness is defined by a peak wavelength of the light and the refractive index of the translucent film. The semiconductor substrate is heated in a temperature range of about 300° C. to about 600° C. A surface of the semiconductor substrate is heated with the light which has a pulse width of about 0.1 ms to about 100 ms.Type: ApplicationFiled: March 27, 2006Publication date: September 28, 2006Inventors: Takayuki Ito, Kouji Matsuo, Naoki Tamaoki, Yoshinori Honguh, Kyoichi Suguro