Patents by Inventor Naoki Yamauchi

Naoki Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9862812
    Abstract: A composition consisting essentially of 90-99 parts by weight of a nitrogen-containing organoxysilane compound and 1-10 parts by weight of an isomer affords an appropriate cure behavior and is useful as paint additive, adhesive, silane coupling agent, textile treating agent, and surface treating agent.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yoichi Tonomura, Tohru Kubota, Masato Kawakami, Naoki Yamauchi, Takayuki Honma
  • Publication number: 20150135996
    Abstract: A composition consisting essentially of 90-99 parts by weight of a nitrogen-containing organoxysilane compound and 1-10 parts by weight of an isomer affords an appropriate cure behavior and is useful as paint additive, adhesive, silane coupling agent, textile treating agent, and surface treating agent.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 21, 2015
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yoichi Tonomura, Tohru Kubota, Masato Kawakami, Naoki Yamauchi, Takayuki Honma
  • Publication number: 20140170733
    Abstract: As a simple and convenient method for promoting the proliferation of algae, a method for cultivating the algae while conducting a procedure S1 for irradiating a red illuminative light to the algae and a procedure S2 for irradiating a blue illuminative light to the algae separately and independently of each other within a certain time period is provided.
    Type: Application
    Filed: March 27, 2012
    Publication date: June 19, 2014
    Applicants: YAMAGUCHI UNIVERSITY, SHOWA DENKO K.K.
    Inventors: Masayoshi Shigyo, Hiroshi Suzuki, Naoki Yamauchi, Hironori Ara, Akihiro Shimokawa, Misato Matsumoto, Yuki Tonooka
  • Publication number: 20140165462
    Abstract: As a plant cultivation method by an artificial light irradiation which is convenient, highly energy efficient, and excellent in growth promoting effect, a plant cultivation method which promotes the plant growth by conducting a step S1 for irradiating a red illuminative light to a plant and a step S2 for irradiating a blue illuminative light to the plant separately and independently of each other within a certain time period. In this plant cultivation method, an extremely remarkable plant growth promoting effect can be obtained by a method as simple as an alternate irradiation with a red illuminative light and a blue illuminative light.
    Type: Application
    Filed: August 3, 2012
    Publication date: June 19, 2014
    Applicants: YAMAGUCHI UNIVERSITY, SHOWA DENKO K.K.
    Inventors: Masayoshi Shigyo, Hiroshi Suzuki, Naoki Yamauchi, Hironori Ara, Akihiro Shimokawa, Misato Matsumoto, Yuki Tonooka
  • Publication number: 20110085724
    Abstract: A paste Pst applied onto a substrate Pb in a predetermined drawing pattern is imaged to acquire the image (step ST1), the outline G of the paste Pst applied onto the substrate Pb is extracted on the basis of the acquired image (step ST2), and the outline length of the paste Pst is calculated from the extracted outline G of the paste Pst (step ST3). The calculated outline length of the paste Pst is compared with a reference range of the outline length determined depending on the drawing pattern of the paste Pst, it is determined whether the outline length of the paste Pst is in the reference range (steps ST4 to ST6), and the application state of the paste is determined (steps ST7 and ST8).
    Type: Application
    Filed: October 5, 2010
    Publication date: April 14, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Shinji SASAGURI, Tadashi SHINOZAKI, Naoki YAMAUCHI
  • Patent number: 7895736
    Abstract: A challenge to be met by the present invention is to provide an electronic component mounting apparatus and an electronic component mounting method that enable a reduction in the frequency of operation required with switching of a component type, to thus enhance productivity.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: March 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Takashi Uchino, Tadashi Shinozaki, Norifumi Eguchi, Naoki Yamauchi, Masao Hidaka, Toru Nakazono
  • Publication number: 20100229378
    Abstract: A challenge to be met by the present invention is to provide an electronic component mounting apparatus and an electronic component mounting method that enable a reduction in the frequency of operation required with switching of a component type, to thus enhance productivity.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 16, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takashi Uchino, Tadashi Shinozaki, Norifumi Eguchi, Naoki Yamauchi, Masao Hidaka, Toru Nakazono
  • Patent number: 6979943
    Abstract: In a cathode ray tube including a panel provided with a phosphor screen, a funnel integrated with the panel, an electron gun disposed inside the funnel, a magnetic shield (1) for shielding an electron beam (5) emitted from the electron gun against an external magnetic field, and a frame (2) for holding the magnetic shield (1), the magnetic shield (1) includes, at a portion to be joined with the frame (2), a bent portion (20) bent toward a tube axis side, and a thickness T of the bent portion (20) at its edge on the tube axis side is 0.08 mm or less. By making the thickness T small, halation that is liable to occur in a cathode ray tube with a large deflection angle can be suppressed because electron beams reflected from an end face (11) and allowed to reach the screen without being shielded by the frame (2) are reduced.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: December 27, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Yamauchi, Hideo Iguchi, Hideharu Omae, Yoshimi Kumei, Tetsuro Ozawa, Yoko Kannan
  • Patent number: 6825601
    Abstract: A color cathode-ray tube includes a shadow mask (20) stretched and held with tension applied thereto in one direction. The shadow mask is made of an Invar material. A stress generated in the shadow mask by the tension is 32 MPa or more in a range of ±20 mm with respect to a center position of the shadow mask in a direction orthogonal to a direction in which the tension is applied, and is 26 MPa or more outside the range. By stretching the shadow mask under this stress condition, magnetic shield characteristics are enhanced, and mislanding of an electron beam can be reduced. As a result, a satisfactory color image display can be obtained.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: November 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Yamauchi, Jun Araya, Hideo Iguchi, Yoshimi Kumei, Masaki Kawasaki, Yoko Kannan
  • Publication number: 20040041513
    Abstract: An internal magnetic shield is joined to a color selection electrode structure including a color selection electrode, a pair of longer side frames supporting the color selection electrode with tension being applied and a pair of shorter side frames joined to the pair of longer side frames. Magnetic shielding members inclined at an inclination angle &thgr; (&thgr;≠0°) to a tube axis are provided on lateral surfaces of shorter sides of the internal magnetic shield. Phosphor screen side edges of the magnetic shielding members are located between the color selection electrode and a plane that passes through color selection electrode side ends of the pair of shorter side frames and is perpendicular to the tube axis. In this manner, magnetic shielding characteristics can be improved against not only a transverse magnetic field but a tube axis magnetic field.
    Type: Application
    Filed: July 22, 2003
    Publication date: March 4, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Kawasaki, Naoki Yamauchi, Kenji Saito, Tetsurou Ozawa
  • Publication number: 20030178929
    Abstract: A color cathode-ray tube includes a shadow mask (20) stretched and held with tension applied thereto in one direction. The shadow mask is made of an Invar material. A stress generated in the shadow mask by the tension is 32 MPa or more in a range of ±20 mm with respect to a center position of the shadow mask in a direction orthogonal to a direction in which the tension is applied, and is 26 MPa or more outside the range. By stretching the shadow mask under this stress condition, magnetic shield characteristics are enhanced, and mislanding of an electron beam can be reduced. As a result, a satisfactory color image display can be obtained.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 25, 2003
    Inventors: Naoki Yamauchi, Jun Araya, Hideo Iguchi, Yoshimi Kumei, Masaki Kawasaki, Yoko Kannan
  • Publication number: 20030155853
    Abstract: In a cathode ray tube including a panel provided with a phosphor screen, a funnel integrated with the panel, an electron gun disposed inside the funnel, a magnetic shield (1) for shielding an electron beam (5) emitted from the electron gun against an external magnetic field, and a frame (2) for holding the magnetic shield (1), the magnetic shield (1) includes, at a portion to be joined with the frame (2), a bent portion (20) bent toward a tube axis side, and a thickness T of the bent portion (20) at its edge on the tube axis side is 0.08 mm or less. By making the thickness T small, halation that is liable to occur in a cathode ray tube with a large deflection angle can be suppressed because electron beams reflected from an end face (11) and allowed to reach the screen without being shielded by the frame (2) are reduced.
    Type: Application
    Filed: March 21, 2003
    Publication date: August 21, 2003
    Inventors: Naoki Yamauchi, Hideo Iguchi, Hideharu Omae, Yoshimi Kumei, Tetsuro Ozawa, Yoko Kannan
  • Patent number: 5428309
    Abstract: A delay circuit includes a semiconductor chip; a first inverter array formed on said semiconductor chip so as to have a number of first inverters so that it provides a number of delay signals; a second inverter array formed on the semiconductor ship so as to have second inverters, each having the same configuration as that of the first inverters, which are connected to form a ring counter; a phase locked lead-in unit for determining a phase difference between an oscillation output of the second inverter array and a basic clock and converting it into a voltage which is applied as power voltage to the first and second inverter arrays.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: June 27, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoki Yamauchi, Hiroshi Kobayashi
  • Patent number: 5353435
    Abstract: In a microcomputer according to the present invention, output pulse levels are stored in bit coles corresponding to respective addresses of a memory circuit which are outputted from a timer circuit which uses a clock as a count source, and each bit output of the memory circuit is latched in synchronism with the clock and outputted to a port output circuit, so as to obtain a plurality of desired phase pulses having different cycles.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: October 4, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirokazu Kitagawa, Naoki Yamauchi
  • Patent number: 5243561
    Abstract: Data in an EEPROM contained in a microcomputer integrated circuit device is erased and re-writing. Upon a detection of a start bit of the data, data of a plurality of bits is accepted in a shift register in response to a clock signal applied from a synchronization circuit. A counter counts clock signals up to the number corresponding to the data of a plurality of bits to inhibit data writing in the shift register. The data accepted in the shift register is temporarily stored as bit parallel data of a plurality of bits in a receiving buffer and selected by a selector to be applied to the EEPROM. The data is written, by a write control circuit, at an address in the EEPROM designated by an address counter.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: September 7, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Yamauchi
  • Patent number: 5097445
    Abstract: A semiconductor integrated circuit with a non-volatile memory capable of electric rewriting of data is disclosed. The circuit is provided with inhibiting means for comparing an address of a write inhibition area of the non-volatile memory and an address from an external or internal CPU and inhibiting the writing of data in the area when the two compared addresses coincide, and also comparing an address of a read inhibition area of the non-volatile memory and an address from an external reader/writer and inhibiting the reading of data from the area when the two compared addresses coincide. It is thus possible to prevent erroneous rewriting of a program or protection-required data due to runaway of CPU and also prevent reading of secret data by a third party. Thus, a microcomputer can be realized, in which a program memory and a data memory both consist of non-volatile memories capable of rewriting of data, and which is very easy to use and has improved reliability and confidential property.
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: March 17, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Yamauchi