Patents by Inventor Naoki Yutani
Naoki Yutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276711Abstract: Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer.Type: GrantFiled: December 14, 2017Date of Patent: April 30, 2019Assignee: Mitsubishi Electric CorporationInventors: Yuji Ebiike, Naoki Yutani
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Publication number: 20180308973Abstract: Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer.Type: ApplicationFiled: December 14, 2017Publication date: October 25, 2018Applicant: Mitsubishi Electric CorporationInventors: Yuji EBIIKE, Naoki YUTANI
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Patent number: 9685566Abstract: A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.Type: GrantFiled: November 9, 2012Date of Patent: June 20, 2017Assignee: Mitsubishi Electric CorporationInventors: Daisuke Chikamori, Yasuhiko Nishio, Naoki Yutani
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Patent number: 9502553Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: July 1, 2015Date of Patent: November 22, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9362391Abstract: It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.Type: GrantFiled: September 21, 2011Date of Patent: June 7, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Eisuke Suekawa, Naoki Yutani, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
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Patent number: 9184307Abstract: A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.Type: GrantFiled: May 29, 2014Date of Patent: November 10, 2015Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Masayuki Imaizumi, Naoki Yutani
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Publication number: 20150303297Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa MIURA, Shuhei NAKATA, Kenichi OHTSUKA, Shoyu WATANABE, Naoki YUTANI
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Patent number: 9105715Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: April 30, 2009Date of Patent: August 11, 2015Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9059193Abstract: A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).Type: GrantFiled: December 27, 2010Date of Patent: June 16, 2015Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ohtsuka, Kenichi Kuroda, Hiroshi Watanabe, Naoki Yutani, Hiroaki Sumitani
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Publication number: 20150060882Abstract: A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.Type: ApplicationFiled: May 29, 2014Publication date: March 5, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro TARUI, Masayuki IMAIZUMI, Naoki YUTANI
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Patent number: 8963276Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.Type: GrantFiled: December 22, 2011Date of Patent: February 24, 2015Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Watanabe, Naoki Yutani, Yoshiyuki Nakaki, Kenichi Ohtsuka
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Publication number: 20140191251Abstract: It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.Type: ApplicationFiled: September 21, 2011Publication date: July 10, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Eisuke Suekawa, Naoki Yutani, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
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Patent number: 8587072Abstract: An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.Type: GrantFiled: March 12, 2012Date of Patent: November 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Yasunori Oritsuki, Naoki Yutani, Yoichiro Tarui
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Patent number: 8569123Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.Type: GrantFiled: September 1, 2009Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
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Publication number: 20130221477Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.Type: ApplicationFiled: December 22, 2011Publication date: August 29, 2013Applicant: Mitsubishi Electric CorporationInventors: Hiroshi Watanabe, Naoki Yutani, Yoshiyuki Nakaki, Kenichi Ohtsuka
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Publication number: 20130196494Abstract: A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.Type: ApplicationFiled: November 9, 2012Publication date: August 1, 2013Inventors: Daisuke CHIKAMORI, Yasuhiko NISHIO, Naoki YUTANI
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Patent number: 8377811Abstract: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C.Type: GrantFiled: August 8, 2008Date of Patent: February 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Kenichi Ohtsuka, Kenichi Kuroda, Shozo Shikama, Naoki Yutani
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Publication number: 20130026494Abstract: An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.Type: ApplicationFiled: March 12, 2012Publication date: January 31, 2013Applicant: Mitsubishi Electric CorporationInventors: Yasunori ORITSUKI, Naoki Yutani, Yoichiro Tarui
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Patent number: 8304901Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.Type: GrantFiled: March 12, 2009Date of Patent: November 6, 2012Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno
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Publication number: 20120241766Abstract: A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).Type: ApplicationFiled: December 27, 2010Publication date: September 27, 2012Applicant: Mitsubishi Electric CorporationInventors: Kenichi Ohtsuka, Kenichi Kuroda, Hiroshi Watanabe, Naoki Yutani, Hiroaki Sumitani