Abstract: A multiplier has an arithmetic unit for multiplying an N-bit multiplicand stored in a second register by an M-bit multiplier stored in a first register according to the Booth's algorithm, and a third register for holding a result or product produced by the arithmetic unit. The first, second, and third registers, and the arithmetic unit are disposed on one substrate surface. The third register is disposed between the arithmetic unit and the second register. The second register is disposed between the third register and a fourth register. The result or product is transferred from the third register directly to the second register or the fourth register, and given as a multiplicand repeatedly to the second register to repeat a multiplication. Since the second and third registers are disposed adjacent to each other, wires required for giving the multiplicand repeatedly to the second register are made shorter.