Abstract: An amplifier includes amplification stages connected in parallel between an input point and an output point and a feedback circuit, wherein the amplification stages each include a transistor configured to amplify a signal supplied from the input point, a harmonic processing unit configured to process harmonics present in an amplified signal output from an output node of the transistor, a connection point between the output node and the harmonic processing unit, and a transmission line connecting the connection point and the output point, wherein the feedback circuit feeds back a signal at the output point or a midway point of the transmission line of a given one of the amplification stages to a first end of a resistor connected to the connection point of the given one of the amplification stages, a second end of the resistor being connected to the connection point of another one of the amplification stages.

Abstract: An amplifier includes amplification stages connected in parallel between an input point and an output point and a feedback circuit, wherein the amplification stages each include a transistor configured to amplify a signal supplied from the input point, a harmonic processing unit configured to process harmonics present in an amplified signal output from an output node of the transistor, a connection point between the output node and the harmonic processing unit, and a transmission line connecting the connection point and the output point, wherein the feedback circuit feeds back a signal at the output point or a midway point of the transmission line of a given one of the amplification stages to a first end of a resistor connected to the connection point of the given one of the amplification stages, a second end of the resistor being connected to the connection point of another one of the amplification stages.

Abstract: A distributed amplifier includes: an input-side transmission line; M amplification circuits; M output-side transmission lines; and a combination circuit configured to combine outputs of the M output-side transmission lines; wherein the input-side transmission line has an input-side serial line formed by connecting in series M×N unit transmission lines each including the same line length, and an input-side terminating resistor, the M amplification circuits each includes N amplifiers and the N amplifiers of the i-th amplification circuit take the input node of the ((k?1) M+i)-th input-side transmission line to be the input, and the output-side transmission line includes an output-side serial line including N transmission lines each being connected in series between the neighboring outputs of the N amplifiers and each having a line width in which the phase of the output of the amplifier in each stage agrees with one another.

Abstract: A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over the nitride semiconductor layers; a first insulating layer disposed over the nitride semiconductor layers, the source electrode and the drain electrode; a second insulating layer disposed over the first insulating layer; a first opening disposed in the second insulating layer and the first insulating layer and between the source electrode and the drain electrode, a portion of the nitride semiconductor layer being exposed in the first opening; a second opening disposed in the second insulating layer and between the source electrode and the drain electrode, a portion of the first insulating layer being exposed in the second opening; and a gate electrode disposed over the second insulating layer to bury the first opening and at least a portion of the second opening.

Abstract: A distributed amplifier includes: an input-side transmission line; M amplification circuits; M output-side transmission lines; and a combination circuit configured to combine outputs of the M output-side transmission lines; wherein the input-side transmission line has an input-side serial line formed by connecting in series MxN unit transmission lines each including the same line length, and an input-side terminating resistor, the M amplification circuits each includes N amplifiers and the N amplifiers of the i-th amplification circuit take the input node of the ((k?1) M+i)-th input-side transmission line to be the input, and the output-side transmission line includes an output-side serial line including N transmission lines each being connected in series between the neighboring outputs of the N amplifiers and each having a line width in which the phase of the output of the amplifier in each stage agrees with one another.

Abstract: A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over the nitride semiconductor layers; a first insulating layer disposed over the nitride semiconductor layers, the source electrode and the drain electrode; a second insulating layer disposed over the first insulating layer; a first opening disposed in the second insulating layer and the first insulating layer and between the source electrode and the drain electrode, a portion of the nitride semiconductor layer being exposed in the first opening; a second opening disposed in the second insulating layer and between the source electrode and the drain electrode, a portion of the first insulating layer being exposed in the second opening; and a gate electrode disposed over the second insulating layer to bury the first opening and at least a portion of the second opening.

Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.

Abstract: A semiconductor device has a semiconductor region including a gate electrode disposed over the semiconductor region, a first electrode portion, a second electrode portion standing substantially perpendicular to a surface of the semiconductor region and a substantially constant dimension in a direction parallel to the surface of the semiconductor region. The semiconductor device has a tapered portion disposed between the first electrode portion and the second electrode portion and has a dimension parallel to the surface of the semiconductor region increasing in the direction from the second electrode portion to the first electrode portion. Further, the semiconductor device includes a source and a drain electrode at both sides of the gate electrode over the semiconductor region and an insulating layer that covers a portion of the surface of the semiconductor region. Additionally, the second electrode portion may be positioned closer to one of the drain electrode and the source electrode.

Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.

Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.