Patents by Inventor Naoko Nakagawa

Naoko Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for designing semiconductor device layout and layout design supporting apparatus
    Publication number: 20090113374
    Abstract: In a layout design method for a semiconductor device having a hard macro, a netlist data of the semiconductor device and a hard macro data are read out from a storage section. An arrangement position of the hard macro is determined from the netlist data and the hard macro data, and an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device is determined based on arrangement restriction data. The interconnection pattern is arranged to extend in the determined extension direction in the specified area.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 30, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Naoko Nakagawa