Patents by Inventor Naoko Sera

Naoko Sera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9087709
    Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 21, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Okada, Shuuichi Kariyazaki, Wataru Shiroi, Masafumi Suzuhara, Naoko Sera
  • Publication number: 20150076684
    Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventors: Makoto Okada, Shuuichi KARIYAZAKI, Wataru SHIROI, Masafumi SUZUHARA, Naoko SERA
  • Patent number: 8922001
    Abstract: A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Okada, Shuuichi Kariyazaki, Wataru Shiroi, Masafumi Suzuhara, Naoko Sera
  • Publication number: 20140159224
    Abstract: A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate.
    Type: Application
    Filed: November 29, 2013
    Publication date: June 12, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Makoto OKADA, Shuuichi KARIYAZAKI, Wataru SHIROI, Masafumi SUZUHARA, Naoko SERA
  • Patent number: 7378745
    Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 27, 2008
    Assignees: NEC Electronics Corporation, Denso Corporation
    Inventors: Akimori Hayashi, Katsunobu Suzuki, Ryuichi Oikawa, Makoto Nakagoshi, Naoko Sera, Tadashi Murai, Chiho Ogihara, Ryohei Kataoka, Koji Kondo, Tomohiro Yokochi
  • Publication number: 20060044735
    Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 2, 2006
    Applicants: NEC ELECTRONICS CORPORATION, DENSO CORPORATION
    Inventors: Akimori Hayashi, Katsunobu Suzuki, Ryuichi Oikawa, Makoto Nakagoshi, Naoko Sera, Tadashi Murai, Chiho Ogihara, Ryohei Kataoka, Koji Kondo, Tomohiro Yokochi