Abstract: A D/A converter can convert M digital signals to M analog signals simultaneously in accordance with used conditions, where M is an integer greater than one. The D/A converter includes a current matrix cell, N weighting cells, and a control circuit, where N is an integer equal to or greater than M. The control circuit divides the current matrix cell in accordance with the number M of digital signals to be D/A converted, and supplies the current matrix cell after the division with specified bits constituting the M digital signals. The control circuit also supplies only the M weighting cells out of the N weighting cells with the remaining bits of the individual M digital signals. The M analog signals are obtained by adding the M currents the current matrix cell produces and the M currents the M weighting cells produce.

Abstract: A D/A converter can convert M digital signals to M analog signals simultaneously in accordance with used conditions, where M is an integer greater than one. The D/A converter includes a current matrix cell, N weighting cells, and a control circuit, where N is an integer equal to or greater than M. The control circuit divides the current matrix cell in accordance with the number M of digital signals to be D/A converted, and supplies the current matrix cell after the division with specified bits constituting the M digital signals. The control circuit also supplies only the M weighting cells out of the N weighting cells with the remaining bits of the individual M digital signals. The M analog signals are obtained by adding the M currents the current matrix cell produces and the M currents the M weighting cells produce.

Abstract: A Veff detector circuit generates input voltages VEP, VEN on the basis of a bias voltage which is fed back so that the difference between these input voltages may be a saturation voltage Veff, and a four-input operational amplifier means receives the input voltages VEP, VEN generated by the Veff detector circuit and generates the bias voltage VB by using reference voltages VERP, VERN which are externally inputted.

Abstract: There is disclosed a start-up circuit (3a) wherein a plurality of NMOSs (Q8 to Q10) are connected in series between the drain of a PMOS (Q1) and a ground potential point (2) and connected at their gate to a power-supply potential point (1), and wherein a voltage drop at the NMOSs (Q8 to Q10) generates a gate potential of a PMOS (Q2) for supplying current to a bias supply circuit (4). By using the voltage drop of the NMOSs (Q8 to Q10) having a small area, the start-up circuit including a CMOS is reduced in layout area.