Patents by Inventor Naoko Yanase
Naoko Yanase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9412825Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.Type: GrantFiled: August 29, 2014Date of Patent: August 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
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Publication number: 20160079410Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.Type: ApplicationFiled: March 3, 2015Publication date: March 17, 2016Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
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Publication number: 20160079373Abstract: A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer.Type: ApplicationFiled: March 2, 2015Publication date: March 17, 2016Inventors: Takeshi UCHIHARA, Wataru SAITO, Takaaki YASUMOTO, Naoko YANASE
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Patent number: 9165922Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.Type: GrantFiled: August 30, 2013Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
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Publication number: 20150263152Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.Type: ApplicationFiled: August 29, 2014Publication date: September 17, 2015Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
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Publication number: 20150263630Abstract: In one embodiment, a power supply circuit includes a first circuit including one or more first switching devices, and a first controller configured to control the first switching devices, the first circuit being configured to output a first voltage. The power supply circuit further includes a second circuit including one or more second switching devices which include a normally-on device, and a second controller configured to control the second switching devices, the second circuit being configured to output a second voltage generated from the first voltage. The second controller transmits a first signal for allowing the first circuit to output the first voltage, based on a value of a voltage or a current at a first node in the second circuit. The first controller allows the first circuit to output the first voltage by controlling the first switching devices in accordance with the first signal.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Inventors: Toshiyuki Naka, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
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Publication number: 20150263101Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono
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Publication number: 20150263700Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
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Publication number: 20150263103Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Tasuku Ono
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Patent number: 9054171Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.Type: GrantFiled: March 7, 2014Date of Patent: June 9, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
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Publication number: 20150076506Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.Type: ApplicationFiled: March 17, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
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Publication number: 20150069468Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
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Patent number: 8916881Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.Type: GrantFiled: September 10, 2013Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoko Yanase, Shingo Masuko, Takaaki Yasumoto, Ryoichi Ohara, Yorito Kakiuchi, Takao Noda, Kenya Sano
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Publication number: 20140335684Abstract: A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants.Type: ApplicationFiled: February 28, 2014Publication date: November 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto MIZUKAMI, Naoko YANASE, Atsuko YAMASHITA
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Publication number: 20140284610Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.Type: ApplicationFiled: August 30, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira YOSHIOKA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Takeshi UCHIHARA, Naoko YANASE, Toshiyuki NAKA, Tetsuya OHNO, Tasuku ONO
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Publication number: 20140283618Abstract: According to one embodiment, a semiconductor device includes a substrate, a semiconductor substrate, an insulating gate field-effect transistor, and a strain gauge unit. The semiconductor substrate is placed on the substrate and has first and second regions. The insulating gate field-effect transistor is provided in the first region of the semiconductor substrate. The strain gauge unit has a long metal resistor, a first insulating film and a second insulating film. The long metal resistor is provided inside of an upper surface of the semiconductor substrate in the second region of the semiconductor substrate. The first insulating film is provided between the semiconductor substrate and the metal resistor and extends up to the upper surface of the semiconductor substrate. The second insulating film is provided above the first insulating film across the metal resistor.Type: ApplicationFiled: September 5, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takaaki Yasumoto, Naoko Yanase, Ryoichi Ohara, Shingo Masuko, Kenya Sano, Yorito Kakiuchi, Takao Noda, Atsuko IIda
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Publication number: 20140014971Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.Type: ApplicationFiled: September 10, 2013Publication date: January 16, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Naoko YANASE, Shingo MASUKO, Takaaki YASUMOTO, Ryoichi OHARA, Yorito KAKIUCHI, Takao NODA, Kenya SANO
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Patent number: 8558244Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.Type: GrantFiled: February 4, 2011Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Naoko Yanase, Shingo Masuko, Takaaki Yasumoto, Ryoichi Ohara, Yorito Kakiuchi, Takao Noda, Kenya Sano
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Publication number: 20110193101Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Naoko YANASE, Shingo Masuko, Takaaki Yasumoto, Ryoichi Ohara, Yorito Kakiuchi, Takao Noda, Kenya Sano
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Patent number: 7770274Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.Type: GrantFiled: November 29, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kenya Sano, Ryoichi Ohara, Naoko Yanase, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo, Hiroshi Toyoda, Masahiko Hasunuma, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki, Hironobu Shibata