Patents by Inventor Naoko Yanase

Naoko Yanase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Patent number: 9165922
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
  • Publication number: 20150263103
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Tasuku Ono
  • Publication number: 20150263630
    Abstract: In one embodiment, a power supply circuit includes a first circuit including one or more first switching devices, and a first controller configured to control the first switching devices, the first circuit being configured to output a first voltage. The power supply circuit further includes a second circuit including one or more second switching devices which include a normally-on device, and a second controller configured to control the second switching devices, the second circuit being configured to output a second voltage generated from the first voltage. The second controller transmits a first signal for allowing the first circuit to output the first voltage, based on a value of a voltage or a current at a first node in the second circuit. The first controller allows the first circuit to output the first voltage by controlling the first switching devices in accordance with the first signal.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Toshiyuki Naka, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono
  • Patent number: 9054171
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20150076506
    Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.
    Type: Application
    Filed: March 17, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
  • Publication number: 20150069468
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Patent number: 8916881
    Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yanase, Shingo Masuko, Takaaki Yasumoto, Ryoichi Ohara, Yorito Kakiuchi, Takao Noda, Kenya Sano
  • Publication number: 20140283618
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a semiconductor substrate, an insulating gate field-effect transistor, and a strain gauge unit. The semiconductor substrate is placed on the substrate and has first and second regions. The insulating gate field-effect transistor is provided in the first region of the semiconductor substrate. The strain gauge unit has a long metal resistor, a first insulating film and a second insulating film. The long metal resistor is provided inside of an upper surface of the semiconductor substrate in the second region of the semiconductor substrate. The first insulating film is provided between the semiconductor substrate and the metal resistor and extends up to the upper surface of the semiconductor substrate. The second insulating film is provided above the first insulating film across the metal resistor.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaaki Yasumoto, Naoko Yanase, Ryoichi Ohara, Shingo Masuko, Kenya Sano, Yorito Kakiuchi, Takao Noda, Atsuko IIda
  • Patent number: 8558244
    Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yanase, Shingo Masuko, Takaaki Yasumoto, Ryoichi Ohara, Yorito Kakiuchi, Takao Noda, Kenya Sano
  • Patent number: 7770274
    Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenya Sano, Ryoichi Ohara, Naoko Yanase, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo, Hiroshi Toyoda, Masahiko Hasunuma, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki, Hironobu Shibata
  • Patent number: 7709999
    Abstract: A thin film piezoelectric resonator includes a substrate having a cavity; a first electrode extending over the cavity; a piezoelectric film placed on the first electrode; and a second electrode placed on the piezoelectric film, the second electrode having a periphery partially overlapping on the cavity and tapered to have an inner angle of 30 degrees or smaller defined by a part of the periphery thereof and a bottom thereof.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: May 4, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Ryoichi Ohara, Kenya Sano, Takaaki Yasumoto, Naoko Yanase
  • Patent number: 7525399
    Abstract: A thin-film piezoelectric resonator includes a substrate, and first and second excitation portions. The substrate includes first and second cavities. The first excitation portion is disposed over the first cavity, and includes a first electrode, a first piezoelectric material and a second electrode laminated successively. An overlapping region among the first electrode, the first piezoelectric material and the second electrode defines a contour of a periphery of the first excitation portion. A first distance is defined as a distance from an end of the first excitation portion to an opening end of the first cavity. The second excitation portion is disposed over the second cavity, and includes a third electrode, a second piezoelectric material and a fourth electrode laminated successively. A second distance is defined as a distance from an end of the second excitation portion to an opening end of the second cavity and different from the first distance.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yanase, Kenya Sano, Takaaki Yasumoto, Ryoichi Ohara, Kazuhiko Itaya
  • Patent number: 7498904
    Abstract: A piezoelectric thin film resonator includes a substrate in which a cavity is formed, a first electrode having a first electrode edge and partly spanning the cavity on the substrate; a piezoelectric layer placed on the first electrode, a second electrode having a second electrode edge and placed on the piezoelectric layer, a resonator unit constituted by an overlapping part of the first electrode, the piezoelectric layer, the second electrode, and the cavity; and a second lead wiring which is integral with the second electrode, extends to the substrate where the cavity is not present, and has a width larger than a part of a peripheral length of the cavity to which the second electrode edge extends. In the piezoelectric thin film resonator, a first length defined by the periphery of the first electrode of the resonator unit is larger than a second length defined by the second electrode edge of the resonator unit.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Ohara, Naoko Yanase, Kenya Sano, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo
  • Publication number: 20090033177
    Abstract: A thin film piezoelectric resonator includes a substrate having a cavity; a first electrode extending over the cavity; a piezoelectric film placed on the first electrode; and a second electrode placed on the piezoelectric film, the second electrode having a periphery partially overlapping on the cavity and tapered to have an inner angle of 30 degrees or smaller defined by a part of the periphery thereof and a bottom thereof.
    Type: Application
    Filed: March 29, 2006
    Publication date: February 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiko Itaya, Ryoichi Ohara, Kenya Sano, Takaaki Yasumoto, Naoko Yanase
  • Patent number: 7463117
    Abstract: A film bulk acoustic-wave resonator encompasses a substrate having a cavity; a bottom electrode partially fixed to the substrate, part of the bottom electrode is mechanically suspended above the cavity; a piezoelectric layer provided on the bottom electrode; and a top electrode provided on the piezoelectric layer having crystal axes oriented along a thickness direction of the piezoelectric layer, a full width at half maximum of the distribution of the orientations of the crystal axes is smaller than or equal to about six degrees.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Ohara, Naoko Yanase, Kazuhiko Itaya, Kenya Sano, Takaaki Yasumoto, Kazuhide Abe, Toshihiko Nagano, Michihiko Nishigaki, Takashi Kawakubo
  • Patent number: 7420320
    Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenya Sano, Ryoichi Ohara, Naoko Yanase, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo, Hiroshi Toyoda, Masahiko Hasunuma, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki, Hironobu Shibata
  • Publication number: 20080072408
    Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya SANO, Ryoichi Ohara, Naoko Yanase, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo, Hiroshi Toyoda, Masahiko Hasunuma, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki, Hironobu Shibata
  • Publication number: 20080074005
    Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya SANO, Ryoichi Ohara, Naoko Yanase, Takaaki Yasumoto, Kazuhiko Itaya, Takashi Kawakubo, Hiroshi Toyoda, Masahiko Hasunuma, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki, Hironobu Shibata