Patents by Inventor Naomi Bizen

Naomi Bizen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7073153
    Abstract: A route of a signal from a starting point pin to an end point pin is searched for in an electronic circuit designed by combining cells which are basic devices entered for use in a designing process. At this time, one or more conditions satisfied by a route to be distinguished from other routes from the starting point pin to the end point pin are set. A route can be distinguished from others depending on whether or not the route satisfies the set condition, and a search for a route from the starting point pin to the end point pin is carried out on each route to be distinguished from others by a condition.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: July 4, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Ikeda, Naomi Bizen
  • Patent number: 6560763
    Abstract: A route searching method is used for circuit design, and includes a step of setting, with respect to each pin, a corresponding flag of a pass flag which indicates that a pin is passed, a searching flag which indicates that a pin is being searched, and a branch flag which indicates that a pin is a branch point, and a step of determining a direction of a route search depending on each flag which is set with respect to each pin.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: May 6, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Sugiyama, Yasunori Abe, Naomi Bizen, Hiroshi Ikeda
  • Publication number: 20020161947
    Abstract: A route of a signal from a starting point pin to an end point pin is searched for in an electronic circuit designed by combining cells which are basic devices entered for use in a designing process. At this time, one or more conditions satisfied by a route to be distinguished from other routes from the starting point pin to the end point pin are set. A route can be distinguished from others depending on whether or not the route satisfies the set condition, and a search for a route from the starting point pin to the end point pin is carried out on each route to be distinguished from others by a condition.
    Type: Application
    Filed: October 22, 2001
    Publication date: October 31, 2002
    Inventors: Hiroshi Ikeda, Naomi Bizen
  • Patent number: 6308305
    Abstract: There are disclosed a method and an apparatus for circuit designing, which enable arranging and wiring operations to be efficiently performed by using indices for arranging and wiring without the occurrence of any error paths. In the method and apparatus for circuit designing, path tracing is performed from one or more tracing start pins for a result of logical designing and the number of passing through each pin of cells to be arranged is counted during the path tracing. Thus, the method and apparatus for circuit designing are suitably used for designing of a circuit such as a LSI or the like, which has been enlarged in size and complex following an advance in a micro fabrication art.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 23, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Sugiyama, Yasunori Abe, Naomi Bizen
  • Patent number: 6240541
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 29, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 5889677
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi