Patents by Inventor Naomi Fukumaki
Naomi Fukumaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230295801Abstract: According to one embodiment, a film forming method includes alternately performing a first process including at least two times of a first sequence and a second process including at least one time of a second sequence. The first sequence includes supplying a film forming gas into a film forming chamber, supplying a first purge gas into the film forming chamber, supplying a first reduction gas into the film forming chamber, and supplying a second purge gas into the film forming chamber, in order, and the second sequence includes supplying a second reduction gas into the film forming chamber, and supplying a third purge gas into the film forming chamber, in order.Type: ApplicationFiled: September 13, 2022Publication date: September 21, 2023Applicant: Kioxia CorporationInventors: Shigeru KINOSHITA, Hiroshi TOYODA, Satoshi WAKATSUKI, Masayuki KITAMURA, Naomi FUKUMAKI
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Publication number: 20230064038Abstract: A semiconductor device includes a substrate and an insulating film formed on the substrate, and an electrode layer comprising molybdenum, formed in contact with the insulating film. The electrode layer has a chlorine concentration gradient such that a first concentration of chlorine in a first portion of the electrode layer closer to the insulating layer is higher than a second concentration of chlorine in a second portion of the electrode layer less closer to the insulating layer.Type: ApplicationFiled: March 4, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Naomi Fukumaki, Ayaka Sakai, Takayuki Beppu
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Publication number: 20230052664Abstract: In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.Type: ApplicationFiled: October 28, 2022Publication date: February 16, 2023Applicant: Kioxia CorporationInventor: Naomi FUKUMAKI
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Patent number: 11515323Abstract: In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.Type: GrantFiled: December 9, 2020Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventor: Naomi Fukumaki
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Publication number: 20220028739Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Applicant: Kioxia CorporationInventors: Satoshi WAKATSUKI, Tomohisa IINO, Naomi FUKUMAKI, Misuzu SATO, Masakatsu TAKEUCHI
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Publication number: 20210407905Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Applicant: Kioxia CorporationInventors: Takashi SHIMIZU, Takashi FUKUSHIMA, Naomi FUKUMAKI, Hiroko TAHARA, Kenichi IDE
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Publication number: 20210296348Abstract: In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.Type: ApplicationFiled: December 9, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventor: Naomi FUKUMAKI
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Publication number: 20210082753Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.Type: ApplicationFiled: March 10, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Satoshi WAKATSUKI, Tomohisa IINO, Naomi FUKUMAKI, Misuzu SATO, Masakatsu TAKEUCHI
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Patent number: 10825770Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.Type: GrantFiled: March 11, 2019Date of Patent: November 3, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu Hatazaki, Hiroko Tahara, Naomi Fukumaki, Masayuki Kitamura, Takashi Ohashi
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Publication number: 20200091081Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.Type: ApplicationFiled: March 11, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu HATAZAKI, Hiroko Tahara, Naomi Fukumaki, Masayuki Kitamura, Takashi Ohashi
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Patent number: 10590532Abstract: In one embodiment, a semiconductor manufacturing apparatus includes first and second tanks configured to store a gas fed from a gas feeder. The apparatus further includes a chamber configured to process a wafer by using the gas fed from the gas feeder, the first tank or the second tank. The apparatus further includes a controller configured to control feeding of the gas to the first tank, the second tank and the chamber.Type: GrantFiled: February 8, 2018Date of Patent: March 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naomi Fukumaki
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Patent number: 10304743Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.Type: GrantFiled: September 12, 2016Date of Patent: May 28, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Naomi Fukumaki, Masaaki Hatano, Seiichi Omoto
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Publication number: 20190071774Abstract: In one embodiment, a semiconductor manufacturing apparatus includes first and second tanks configured to store a gas fed from a gas feeder. The apparatus further includes a chamber configured to process a wafer by using the gas fed from the gas feeder, the first tank or the second tank. The apparatus further includes a controller configured to control feeding of the gas to the first tank, the second tank and the chamber.Type: ApplicationFiled: February 8, 2018Publication date: March 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Naomi Fukumaki
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Patent number: 10096485Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.Type: GrantFiled: June 23, 2015Date of Patent: October 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naomi Fukumaki
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Publication number: 20170352622Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.Type: ApplicationFiled: September 12, 2016Publication date: December 7, 2017Applicant: Toshiba Memory CorporationInventors: Naomi FUKUMAKI, Masaaki HATANO, Seiichi OMOTO
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Publication number: 20160247755Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.Type: ApplicationFiled: June 23, 2015Publication date: August 25, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naomi FUKUMAKI
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Patent number: 9379178Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.Type: GrantFiled: August 26, 2015Date of Patent: June 28, 2016Assignee: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Publication number: 20150372074Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.Type: ApplicationFiled: August 26, 2015Publication date: December 24, 2015Inventors: Youichi YAMAMOTO, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Patent number: 9142609Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.Type: GrantFiled: January 12, 2011Date of Patent: September 22, 2015Assignee: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
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Patent number: 8440521Abstract: A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.Type: GrantFiled: June 27, 2011Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Naomi Fukumaki, Eiji Hasegawa, Toshihiro Iizuka, Ichiro Yamamoto