Patents by Inventor Naomi Masuda
Naomi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9437573Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.Type: GrantFiled: December 20, 2013Date of Patent: September 6, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Naomi Masuda, Masataka Hoshino, Ryota Fukuyama
-
Patent number: 9418940Abstract: Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure.Type: GrantFiled: April 25, 2008Date of Patent: August 16, 2016Assignee: Cypress Semiconductor CorporationInventors: Masataka Hoshino, Masahiko Harayama, Koji Taya, Naomi Masuda, Masanori Onodera, Ryota Fukuyama
-
Patent number: 9385014Abstract: A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.Type: GrantFiled: December 7, 2010Date of Patent: July 5, 2016Assignee: Cypress Semiconductor CorporationInventor: Naomi Masuda
-
Patent number: 9362173Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: GrantFiled: October 18, 2011Date of Patent: June 7, 2016Assignee: Nantong Fujitsu Microelectronics Co., Ltd.Inventors: Lei Shi, Yujuan Tao, Guohua Gao, Naomi Masuda, Koichi Meguro
-
Patent number: 9293441Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: October 4, 2011Date of Patent: March 22, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
-
Patent number: 8883627Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: GrantFiled: October 18, 2011Date of Patent: November 11, 2014Assignee: Nantong Fujitsu Microelectronics Co., Ltd.Inventors: Lei Shi, Guohua Gao, Yujuan Tao, Naomi Masuda, Koichi Meguro
-
Patent number: 8796864Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: GrantFiled: June 14, 2013Date of Patent: August 5, 2014Assignee: Spansion LLCInventors: Naomi Masuda, Koji Taya
-
Patent number: 8765529Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.Type: GrantFiled: October 30, 2013Date of Patent: July 1, 2014Assignee: Spansion LLCInventor: Naomi Masuda
-
Publication number: 20140113411Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: Spansion LLCInventors: Naomi MASUDA, Masataka HOSHINO, Ryota FUKUYAMA
-
Publication number: 20140094001Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.Type: ApplicationFiled: October 30, 2013Publication date: April 3, 2014Applicant: Spansion LLCInventor: Naomi MASUDA
-
Patent number: 8637986Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.Type: GrantFiled: October 22, 2008Date of Patent: January 28, 2014Assignee: Spansion LLCInventors: Naomi Masuda, Masataka Hoshino, Ryota Fukuyama
-
Patent number: 8598717Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.Type: GrantFiled: December 21, 2007Date of Patent: December 3, 2013Assignee: Spansion LLCInventor: Naomi Masuda
-
Publication number: 20130277834Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Naomi MASUDA, Koji TAYA
-
Publication number: 20130280904Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: ApplicationFiled: October 18, 2011Publication date: October 24, 2013Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.Inventors: Lei Shi, Guohua Gao, Yujuan Tao, Naomi Masuda, Koichi Meguro
-
Publication number: 20130224910Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: ApplicationFiled: October 18, 2011Publication date: August 29, 2013Applicant: NANTONG FUJITSU MOCROELECTRONICS CO., LTD.Inventors: Lei Shi, Yujuan Tao, Guohua Gao, Naomi Masuda, Koichi Meguro
-
Patent number: 8486756Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: GrantFiled: December 23, 2008Date of Patent: July 16, 2013Assignee: Spansion LLCInventors: Naomi Masuda, Koji Taya
-
Patent number: 8446015Abstract: A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12, a second metal 16 provided in the resin 12 over the first metal 14, and being exposed on an upper surface of the resin 12, and a first wire 18 coupling the first semiconductor chip 10 to the first metal 14 and the second metal 16. The first wire 18 is coupled to the first metal 14 and the second metal 16 so as to be sandwiched therebetween.Type: GrantFiled: January 27, 2011Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Naomi Masuda, Kouichi Meguro
-
Patent number: 8274158Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective one of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.Type: GrantFiled: September 8, 2010Date of Patent: September 25, 2012Assignee: Spansion LLCInventors: Junichi Kasai, Junji Tanaka, Naomi Masuda
-
Publication number: 20120049362Abstract: A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12, a second metal 16 provided in the resin 12 over the first metal 14, and being exposed on an upper surface of the resin 12, and a first wire 18 coupling the first semiconductor chip 10 to the first metal 14 and the second metal 16. The first wire 18 is coupled to the first metal 14 and the second metal 16 so as to be sandwiched therebetween.Type: ApplicationFiled: January 27, 2011Publication date: March 1, 2012Inventors: Naomi MASUDA, Kouichi MEGURO
-
Publication number: 20120025364Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: ApplicationFiled: October 4, 2011Publication date: February 2, 2012Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA