Abstract: An apparatus is provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided is an apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided is an apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided is an apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: A method and apparatus are provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are a method and apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are a method and apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are a method and apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: An improved RIE process is disclosed for etching one or more openings in a layer of an oxide of silicon on a semiconductor wafer characterized by a contact angle of at least 80.degree., with respect to the plane of the oxide layer, and highly selective to silicon which comprises flowing an inert gas and CHF.sub.3 into an RIE chamber while maintaining respective gas flows within a range of from about 15 to about 185 sccm of inert gas and from about 15 to about 60 sccm of CHF.sub.3, with a total gas flow not exceeding about 200 sccm, and a ratio of inert gas to CHF.sub.3 ranging from about 1:1 to about 10:1. A plasma is maintained in the RIE chamber during the gas flow at a power level within a range of from about 400 to about 1000 watts. In a preferred embodiment, CF.sub.4 gas is also flowed into the RIE chamber within a range of from about 1 to about 10 sccm to control the selectivity of the etch to silicon, and the wafer is immersed in a magnetic field of 1 to 120 gauss during the etching process.