Patents by Inventor Naomi Yamazaki
Naomi Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190343796Abstract: An object of the present invention is to provide a composition for external use having an improved skin permeability of 1-(3-(2-(1-benzothiophen-5-yl)ethoxy)propyl)azetidin-3-ol or a salt thereof. The present invention provides a composition for external use comprising 1-(3-(2-(1-benzothiophen-5-yl)ethoxy)propyl)azetidin-3-ol or a salt thereof, one or more solvents selected from the group consisting of alcohols, sulfoxides and amides, and a permeation enhancer.Type: ApplicationFiled: December 28, 2017Publication date: November 14, 2019Applicant: FUJIFILM Toyama Chemical Co., Ltd.Inventors: Naomi YAMAZAKI, Masaki NORO, Shigetomo TSUJIHATA
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Publication number: 20180177800Abstract: Provided is a composition for percutaneous absorption containing testosterone and one or more organic solvents selected from the group consisting of propylene glycol, 1,3-butylene glycol, dipropylene glycol and polyethylene glycol, in which a total content of the organic solvents with respect to a total amount of the composition for percutaneous absorption is from 60% by mass to 90% by mass, and in which a content of a monohydric alcohol having 2 to 4 carbon atoms with respect to the total amount of the composition for percutaneous absorption is equal to or less than 10% by mass.Type: ApplicationFiled: February 23, 2018Publication date: June 28, 2018Inventors: Shirou SONOKE, Yasuyuki IZUMI, Naomi YAMAZAKI
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Patent number: 7731083Abstract: A terminal device, in an information collection system in which the terminal device and an information collection device are connected, which reads question information from a question information storage section storing question information, as questions the responses to which are to be provided to the information collection device, and after power to the terminal device has been turned on, or based on a state of usage, receives the input of response information, as responses corresponding to output question information, and transmits the input response information to the information collection device.Type: GrantFiled: November 8, 2005Date of Patent: June 8, 2010Assignee: Seiko Epson CorporationInventors: Nobutoshi Terakawa, Naomi Yamazaki
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Publication number: 20060106875Abstract: A terminal device, in an information collection system in which the terminal device and an information collection device are connected, which reads question information from a question information storage section storing question information, as questions the responses to which are to be provided to the information collection device, and after power to the terminal device has been turned on, or based on a state of usage, receives the input of response information, as responses corresponding to output question information, and transmits the input response information to the information collection device.Type: ApplicationFiled: November 8, 2005Publication date: May 18, 2006Inventors: Nobutoshi Terakawa, Naomi Yamazaki
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Patent number: 6961343Abstract: An input data (input frame) is sequentially stored in memory in time slot units. A counter counts the number of input pulses of a clock synchronous with the time slot of the input frame, outputs the count value as a write address to the memory, and outputs it as a read address to the memory. A processor in a cross-connection device preliminarily writes to the memory data indicating switching information of a time slot. The memory outputs the data stored at an address input from the counter as a read address to the memory. The memory outputs data of a time slot of an input frame stored at the address as time slot data of an output frame.Type: GrantFiled: October 4, 1999Date of Patent: November 1, 2005Assignee: Fujitsu LimitedInventor: Naomi Yamazaki
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Patent number: 6622060Abstract: The present invention relates to a mounting-state display apparatus for displaying the mounting-states of devices. Particularly, the present invention provides a mounting-state display apparatus enabled to automatically generate a display, indicating the mounting-states of various kinds of packages in the devices, which is not limited to a specific device, by using an NE-OPS for managing the devices. This mounting-state display apparatus comprises a device component database, for holding device components, which represents a mounting state of an arbitrary one of the devices as original picture elements of a minimum configuration required to indicate a mounting-state display and an application program portion for accessing the device component database and for generating a display indicating the mounting state of a specific one of the devices by performing operations of placing the original picture elements and changing the size thereof.Type: GrantFiled: July 19, 2000Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventor: Naomi Yamazaki
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Publication number: 20030137533Abstract: A method of performing a control operation on a target apparatus in a network including a step of creating a function information file describing control functions of the target apparatus, a step of forming a control window by gathering control functions stored in the function information file, a step of storing the control window in a performance information file, and a step of performing control operations by retrieving the control window from the performance information file. The method prepares beforehand the function information file that stores information of various functions of the target apparatuses and their platforms. The window for controlling the target apparatuses can be created by cutting and pasting necessary control functions from the function information file to the control window. The control functions created in the window are stored in the performance information file. A function performance unit retrieves a control function to perform the control operation accordingly.Type: ApplicationFiled: December 24, 2002Publication date: July 24, 2003Inventors: Naomi Yamazaki, Yosuke Katagiri, Akihiko Hanawa, Masato Miyata, Hideki Dake
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Patent number: 6493775Abstract: A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing circuit, a system bus controller for the processor and a system bus controller for the memory or a system bus controller for the processing circuit access the system bus within an accessible minimum time with each of input/output signals. When the DMAC transfers data to the memory or the processing circuit, a system bus controller for the DMAC and the system bus controller for the memory or the system bus controller for the processing circuit access the system bus within the accessible minimum time with each of the input/output signals.Type: GrantFiled: January 19, 1999Date of Patent: December 10, 2002Assignee: Fujitsu LimitedInventors: Naomi Yamazaki, Ryoetsu Nakajima, Masumi Fujino
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Publication number: 20020069311Abstract: A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing circuit, a system bus controller for the processor and a system bus controller for the memory or a system bus controller for the processing circuit access the system bus within an accessible minimum time with each of input/output signals. When the DMAC transfers data to the memory or the processing circuit, a system bus controller for the DMAC and the system bus controller for the memory or the system bus controller for the processing circuit access the system bus within the accessible minimum time with each of the input/output signals.Type: ApplicationFiled: January 19, 1999Publication date: June 6, 2002Inventors: NAOMI YAMAZAKI, RYOETSU NAKAJIMA, MASUMI FUJINO
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Patent number: 6029210Abstract: When normal data is written to a desired address in a DRAM, a guarantee bit comparing/generating circuit sets the value of guarantee bit data stored at the address corresponding to the desired address in a DRAM as a value indicating that the normal data has been written. Since the guarantee bit data stored at each address in the DRAM always becomes "000" or "111" immediately after power is turned on, the above described value indicating that the normal data has been written is set as a value other than "000" and "111". Thereafter, if the value of the guarantee bit data stored at the address corresponding to the desired address in the DRAM indicates that the normal data has been written when the normal data is read from the desired address in the DRAM, the normal data read from the DRAM is output to a data bus. Otherwise, the fixed value "0" is output to the data bus as read data.Type: GrantFiled: December 16, 1997Date of Patent: February 22, 2000Assignee: Fujitsu LimitedInventor: Naomi Yamazaki
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Patent number: 5625772Abstract: A gray-scale display device such as a general display for a personal computer or work station, a laser printer or a color printer. A gray-scale font generating apparatus used in the display device includes an input unit for inputting the information representative of a font code, and control unit for acquiring a blend ratio in accordance with the ratio of a font area and a background area in the contour of the shape data of the font corresponding to the information representative of a font code, and making the gradation display of the font with the blend ratio thus acquired. Since the blend ratio is acquired without using work memory, a gray-scale font can be created and output at high speed.Type: GrantFiled: August 7, 1992Date of Patent: April 29, 1997Assignee: Hitachi, Ltd.Inventors: Naomi Yamazaki, Atsushi Kawabata
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Patent number: 5442777Abstract: A firmware trace data acquisition method is constituted such that there are provided a monitoring part for monitoring firmware processes and a DMA part for transferring data to a trace data storing part in accordance with an instruction from the monitoring part, such that labels are attached to the plurality of process modules stored in a firmware storing part, and such that each of the process modules activated notifies the monitoring part of the label attached to itself. The monitoring part latches the label that it is notified of and monitors the execution of the corresponding process such that, when an abnormality is detected during the execution, the monitoring part controls the DMA part so as to transfer detailed data, derived from the process module corresponding to the label latched, to the trace data storing part, and such that, when there is no abnormality detected, the monitoring part allows the DMA part to transfer the latched label to the trace data storing part.Type: GrantFiled: February 25, 1994Date of Patent: August 15, 1995Assignee: Fujitsu LimitedInventors: Ryoetsu Nakajima, Naomi Yamazaki, Takumi Maruyama, Kiyoshi Sugita