Patents by Inventor Naomichi Ohashi

Naomichi Ohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150187977
    Abstract: To provide a solar cell module formed by a lamination structure in which a lower sealing portion (101) having a total light reflectance of 50% or more is arranged on a back sheet (106) side with respect to a solar cell device (103) and an upper sealing portion (102) having a total light transmittance of 50% or more is arranged on a solar-light irradiation surface side with respect to a solar cell device (103), and a porous body (104) is interposed between the lower sealing portion (101) and the solar cell device (103). To further provide a solar cell module in which an opening is formed in the porous body and the solar cell device is positioned in the opening.
    Type: Application
    Filed: June 18, 2013
    Publication date: July 2, 2015
    Inventors: Hideyuki Tsujimura, Naomichi Ohashi
  • Patent number: 8940198
    Abstract: A conductive adhesive includes 10 to 90 wt % of Sn—Bi system solder powder and the remainder of an adhesive containing organic acid, and the Sn—Bi system solder powder is composed of solder particles having a particle size L1 of 20 to 30 ?m and solder particles having a particle size L2 of 8 to 12 ?m, and a mixing ratio of the Sn—Bi system solder powder is such that the solder particles having a particle size of 20 to 30 ?m occupy 40 to 90 wt % with respect to the whole solder powder, and the remainder is occupied by solder particles having a particle size of 8 to 12 ?m.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Arata Kishi, Naomichi Ohashi, Atsushi Yamaguchi
  • Publication number: 20140120663
    Abstract: A semiconductor package component (3) is mounted on a substrate (1) in such a manner that an electrode (2) of the substrate (1) and an electrode of the semiconductor package component (3) are brought into contact with each other through a joining material (4). A reinforcing adhesive (5c) is applied between the substrate (1) and the outer surface of the semiconductor package component (3). Then, reflow is performed to melt the joining metal (4) with the reinforcing adhesive (5c) uncured. After the reinforcing adhesive (5c) is cured, the joining metal (4) is solidified.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 1, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Naomichi OHASHI, Atsushi YAMAGUCHI, Arata KISHI, Masato UDAKA, Seiji TOKII
  • Patent number: 8664773
    Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 4, 2014
    Assignee: Panasonic Corporation
    Inventors: Atsushi Yamaguchi, Hideyuki Tsujimura, Hiroe Kowada, Ryo Kuwabara, Naomichi Ohashi
  • Publication number: 20140049930
    Abstract: In a case where a first mounted substrate to which a semiconductor element is bounded by solder is mounted on a second substrate, connection strength becomes low, when the first mounted substrate is bonded to the second substrate by using a solder having a low melting point. A mounted structure, in which a first mounted substrate on which a semiconductor element is bonded by using a first solder having a melting point of 217° C. or more, is mounted on a second substrate, includes plural bonding parts bonding the first mounted substrate to the second substrate; and a reinforcing member formed around the bonding part. Each of the bonding parts contains a second solder having a melting point, that is lower than the melting point of the first solder, and a space exists, in which the reinforcing members do not exist, between the bonding parts neighboring each other.
    Type: Application
    Filed: April 2, 2012
    Publication date: February 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Atsushi Yamaguchi, Hisahiko Yoshida, Arata Kishi, Naomichi Ohashi
  • Patent number: 8540903
    Abstract: Disclosed is an electrically conductive paste which enables to reduce the level of void growth in a conducting pathway formed in a joint part produced after curing the electrically conductive paste in the implementation of an electronic component on a circuit board by using the electrically conductive paste, and which contains a reduced amount of a viscosity-adjusting/thixotropy-imparting additive. Two Sn-containing low-melting-point alloy particles having different melting points and different average particle diameters are selected as electrically conductive filler components to be used in an electrically conductive paste, and the two alloy particles are mixed at a predetermined ratio for use.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 24, 2013
    Assignee: Panasonic Corporation
    Inventors: Takayuki Higuchi, Hidenori Miyakawa, Atsushi Yamaguchi, Arata Kishi, Naomichi Ohashi
  • Patent number: 8450859
    Abstract: A semiconductor device mounted structure includes a semiconductor device having a plurality of first electrodes, a circuit board having a plurality of second electrodes, a plurality of bumps respectively formed on the plurality of first electrodes, a plurality of bonding members respectively positioned between the bumps and the second electrodes to electrically connect the first electrodes to the second electrodes via the bumps, and a plurality of reinforcing resin members respectively positioned around the bonding members so as to cover at least the bonding members and bonding regions between the bonding members and the bumps. Adjacent reinforcing resin members are spaced away from each other so as not to have contact with each other without being in contact with the semiconductor device. This semiconductor device mounted structure enhances the reliability of joints in impact resistance and makes it easy to repair it.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: May 28, 2013
    Assignee: Panasonic Corporation
    Inventors: Naomichi Ohashi, Shigeaki Sakatani, Arata Kishi, Atsushi Yamaguchi, Hidenori Miyakawa
  • Publication number: 20120299202
    Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: Panasonic Corporation
    Inventors: Atsushi YAMAGUCHI, Hideyuki TSUJIMURA, Hiroe KOWADA, Ryo KUWABARA, Naomichi OHASHI
  • Patent number: 8182923
    Abstract: A conductive paste includes a filler component and a flux component; the filler component including a first conductive filler and a second conductive filler having different melting points, and the melting point of the first conductive filler being higher than the melting point of the second conductive filler by 20° C. or more; the flux component including a first flux and a second flux having different melting points, the melting point of the first flux being higher than the melting point of the second flux, and the melting point of the first flux being higher than the melting point of the second conductive filler by 15° C. to 45° C.; and the melting point of the second flux being equal to or less than the melting point of the second conductive filler.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: May 22, 2012
    Assignee: Panasonic Corporation
    Inventors: Naomichi Ohashi, Hidenori Miyakawa, Atsushi Yamaguchi, Arata Kishi, Takayuki Higuchi
  • Publication number: 20120073869
    Abstract: A conductive adhesive includes 10 to 90 wt % of Sn—Bi system solder powder and the remainder of an adhesive containing organic acid, and the Sn—Bi system solder powder is composed of solder particles having a particle size L1 of 20 to 30 ?m and solder particles having a particle size L2 of 8 to 12 ?m, and a mixing ratio of the Sn—Bi system solder powder is such that the solder particles having a particle size of 20 to 30 ?m occupy 40 to 90 wt % with respect to the whole solder powder, and the remainder is occupied by solder particles having a particle size of 8 to 12 ?m.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 29, 2012
    Applicant: Panasonic Corporation
    Inventors: Arata KISHI, Naomichi OHASHI, Atsushi YAMAGUCHI
  • Publication number: 20110108997
    Abstract: A semiconductor package component (3) is mounted on a substrate (1) in such a manner that an electrode (2) of the substrate (1) and an electrode of the semiconductor package component (3) are brought into contact with each other through a joining material (4). A reinforcing adhesive (5c) is applied between the substrate (1) and the outer surface of the semiconductor package component (3). Then, reflow is performed to melt the joining metal (4) with the reinforcing adhesive (5c) uncured. After the reinforcing adhesive (5c) is cured, the joining metal (4) is solidified.
    Type: Application
    Filed: April 19, 2010
    Publication date: May 12, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Naomichi Ohashi, Atsushi Yamaguchi, Arata Kishi, Masato Udaka, Seiji Tokii
  • Publication number: 20110095423
    Abstract: A semiconductor device mounted structure includes a semiconductor device having a plurality first electrodes, a circuit board having a plurality of second electrodes, a plurality of bumps respectively formed on the plurality of first electrodes, a plurality of bonding members respectively positioned between the bumps and the second electrodes to electrically connect the first electrodes to the second electrodes via the bumps, and a plurality of reinforcing resin members respectively positioned around the bonding members so as to cover at least the bonding members and bonding regions between the bonding members and the bumps. Adjacent reinforcing resin members are spaced away from each other so as not to have contact with each other without being in contact with the semiconductor device. This semiconductor device mounted structure enhances the reliability of joints in impact resistance and makes it easy to repair it.
    Type: Application
    Filed: October 27, 2009
    Publication date: April 28, 2011
    Inventors: Naomichi Ohashi, Shigeaki Sakatani, Arata Kishi, Atsushi Yamaguchi, Hidenori Miyakawa
  • Publication number: 20110049439
    Abstract: Disclosed is an electrically conductive paste which enables to reduce the level of void growth in a conducting pathway formed in a joint part produced after curing the electrically conductive paste in the implementation of an electronic component on a circuit board by using the electrically conductive paste, and which contains a reduced amount of a viscosity-adjusting/thixotropy-imparting additive. Two Sn-containing low-melting-point alloy particles having different melting points and different average particle diameters are selected as electrically conductive filler components to be used in an electrically conductive paste, and the two alloy particles are mixed at a predetermined ratio for use.
    Type: Application
    Filed: November 21, 2008
    Publication date: March 3, 2011
    Inventors: Takayuki Higuchi, Hidenori Miyakawa, Atsushi Yamaguchi, Arata Kishi, Naomichi Ohashi
  • Publication number: 20100101845
    Abstract: An electronic device manufacturing method includes: setting a solder material on electrodes of a first circuit assembly; setting a resin having a flux action on one surface of a second circuit assembly so as to entirely cover solder bumps formed on the one surface of the second circuit assembly; setting the second circuit assembly on the first circuit assembly via the resin so that the solder material set on the electrodes of the first circuit assembly and the solder bumps of the second circuit assembly are put into contact with each other; and applying thermal energy to connecting portions between the solder material and the solder bumps and to the resin. By carrying out these processes, an electronic device in which the first circuit assembly and the second circuit assembly are joined together and in which their junction portions are sealed by the resin is manufactured. As a result, in the electronic device, junction reliability can be improved.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 29, 2010
    Inventors: Arata Kishi, Naomichi Ohashi, Atsushi Yamaguchi, Seiji Tokii, Masato Udaka
  • Publication number: 20090269598
    Abstract: A conductive paste includes a filler component and a flux component; the filler component including a first conductive filler and a second conductive filler having different melting points, and the melting point of the first conductive filler being higher than the melting point of the second conductive filler by 20° C. or more; the flux component including a first flux and a second flux having different melting points, the melting point of the first flux being higher than the melting point of the second flux, and the melting point of the first flux being higher than the melting point of the second conductive filler by 15° C. to 45° C.; and the melting point of the second flux being equal to or less than the melting point of the second conductive filler.
    Type: Application
    Filed: April 21, 2009
    Publication date: October 29, 2009
    Inventors: Naomichi OHASHI, Hidenori MIYAKAWA, Atsushi YAMAGUCHI, Arata KISHI, Takayuki HIGUCHI