Patents by Inventor Naomu Kitano
Naomu Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10297797Abstract: A method for manufacturing a display device includes forming an insulating layer embedding a transistor arranged on a substrate, forming a first electrode electrically connected with the transistor above the insulating layer, forming a partition wall layer having an opening part covering a periphery edge part of the first electrode and exposing an inner side region of the first electrode, forming an organic layer including an organic electroluminescent material above the first electrode, forming a second electrode above the partition layer and the organic layer, and forming a sealing layer above the second electrode. Deposition of the second electrode includes a film deposition step of an electrode layer having a thinner film thickness than a target film thickness of the second electrode, and a waiting step after completion of the deposition step of the electrode layer.Type: GrantFiled: March 5, 2018Date of Patent: May 21, 2019Assignee: Japan Display Inc.Inventors: Naomu Kitano, Keisuke Ono
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Publication number: 20180261803Abstract: A method for manufacturing a display device includes forming an insulating layer embedding a transistor arranged on a substrate, forming a first electrode electrically connected with the transistor above the insulating layer, forming a partition wall layer having an opening part covering a periphery edge part of the first electrode and exposing an inner side region of the first electrode, forming an organic layer including an organic electroluminescent material above the first electrode, forming a second electrode above the partition layer and the organic layer, and forming a sealing layer above the second electrode. Deposition of the second electrode includes a film deposition step of an electrode layer having a thinner film thickness than a target film thickness of the second electrode, and a waiting step after completion of the deposition step of the electrode layer.Type: ApplicationFiled: March 5, 2018Publication date: September 13, 2018Inventors: Naomu Kitano, Keisuke Ono
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Patent number: 9437702Abstract: It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer.Type: GrantFiled: July 10, 2014Date of Patent: September 6, 2016Assignee: CANON ANELVA CORPORATIONInventors: Akira Matsuo, Yohsuke Shibuya, Naomu Kitano, Eitaroh Morimoto, Koji Yamazaki, Yu Sato, Takuya Seino
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Publication number: 20140319676Abstract: It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer.Type: ApplicationFiled: July 10, 2014Publication date: October 30, 2014Inventors: Akira MATSUO, Yohsuke SHIBUYA, Naomu KITANO, Eitaroh MORIMOTO, Koji YAMAZAKI, Yu SATO, Takuya SEINO
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Patent number: 8835296Abstract: The present invention provides an electronic component manufacturing method including a step of embedding a metal film. An embodiment of the present invention includes a first step of depositing a barrier layer containing titanium nitride on an object to be processed on which a concave part is formed and a second step of filling a low-melting-point metal directly on the barrier layer under a temperature condition allowing the low-melting-point metal to flow, by a PCM sputtering method while forming a magnetic field by a magnet unit including plural magnets which are arranged at grid points of a polygonal grid so as to have different polarities between the neighboring magnets.Type: GrantFiled: June 20, 2011Date of Patent: September 16, 2014Assignee: Canon Anelva CorporationInventors: Shunichi Wakayanagi, Takayuki Saito, Takuya Seino, Akira Matsuo, Koji Yamazaki, Eitaro Morimoto, Yohsuke Shibuya, Yu Sato, Naomu Kitano
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Patent number: 8786031Abstract: The present invention provides a metal nitride film that realizes an intended effective work function (for example, a high effective work function) and has EOT exhibiting no change or a reduced change, a semiconductor device using the metal nitride film, and a manufacturing method of the semiconductor device. The metal nitride film according to an embodiment of the present invention contains Ti, Al and N, wherein the metal nitride film has such molar fractions of Ti, Al and N as (N/(Ti+Al+N)) of 0.53 or more, (Ti/(Ti+Al+N)) of 0.32 or less, and (Al/(Ti+Al+N)) of 0.15 or less.Type: GrantFiled: February 28, 2011Date of Patent: July 22, 2014Assignee: Canon Anelva CorporationInventors: Takashi Nakagawa, Naomu Kitano
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Patent number: 8669624Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.Type: GrantFiled: July 26, 2012Date of Patent: March 11, 2014Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
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Publication number: 20130285158Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.Type: ApplicationFiled: July 26, 2012Publication date: October 31, 2013Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
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Patent number: 8524617Abstract: A method for manufacturing a dielectric film having a high dielectric constant is provided. The method is a method for forming, on a substrate, a dielectric film including a metal oxide containing O and elements A and B, wherein the element A comprises Hf or a mixture of Hf and Zr and the element B comprises Al or Si, which includes the steps of: forming a metal oxide having an amorphous structure which has a molar ratio between element A and element B, B/(A+B) of 0.02?(B/(A+B))?0.095 and a molar ratio between element A and O, O/A of 1.0<(O/A)<2.0; and annealing the metal oxide having the amorphous structure at 700° C. or more to form a metal oxide containing a crystal phase with a cubic crystal content of 80% or more.Type: GrantFiled: February 26, 2010Date of Patent: September 3, 2013Assignee: Canon Anelva CorporationInventors: Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
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Patent number: 8481382Abstract: The present invention provides a method and apparatus for manufacturing a semiconductor device using a PVD method and enabling achievement of a desired effective work function and reduction in leak current without increasing an equivalent oxide thickness. A method for manufacturing a semiconductor device in an embodiment of the present invention includes the steps of: preparing a substrate on which an insulating film having a relative permittivity higher than that of a silicon oxide film is formed; and depositing a metal nitride film on the insulating film. The metal nitride depositing step is a step of sputtering deposition in an evacuatable chamber using a metal target and a cusp magnetic field formed over a surface of the metal target by a magnet mechanism in which magnet pieces are arranged as grid points in such a grid form that the adjacent magnet pieces have their polarities reversed from each other.Type: GrantFiled: November 13, 2012Date of Patent: July 9, 2013Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takuya Seino, Akira Matsuo, Yu Sato, Eitaro Morimoto
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Patent number: 8415753Abstract: This invention provides a semiconductor device having a field effect transistor comprising a gate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1<X1 <1.8, and in the second metal nitride layer 8, the molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X2 is 1.Type: GrantFiled: April 28, 2010Date of Patent: April 9, 2013Assignee: Canon Anelva CorporationInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
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Patent number: 8324608Abstract: In a variable resistance nonvolatile storage element, an electrode suitable for a variable resistance operation and formed of a metallic nitride layer containing Ti and N is provided. In a nonvolatile storage device including: a first electrode; a second electrode; and a variable resistance layer which is sandwiched between the first electrode and the second electrode and in which a resistance value changes to two different resistance states, at least one of the first electrode and the second electrode is an electrode including a metallic nitride layer containing at least Ti and N, and a mole ratio (N/Ti ratio) between Ti and N in at least a part of the metallic nitride layer, the part being in contact with the variable resistance layer is 1.15 or more and a film density is 4.7 g/cc or more.Type: GrantFiled: April 19, 2012Date of Patent: December 4, 2012Assignee: Canon Anelva CorporationInventors: Takashi Nakagawa, Eun-mi Kim, Yuichi Otani, Naomu Kitano
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Patent number: 8288234Abstract: To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×10?1 A/cm2 or less, (3) suppress hysteresis caused by the generation of fixed charges, and (4) prevent an increase in EOT even if heat treatment at 700° C. or more is performed and obtain excellent heat resistance.Type: GrantFiled: July 21, 2010Date of Patent: October 16, 2012Assignee: Canon Anelva CorporationInventors: Takuya Seino, Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
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Publication number: 20120248397Abstract: In a variable resistance nonvolatile storage element, an electrode suitable for a variable resistance operation and formed of a metallic nitride layer containing Ti and N is provided. In a nonvolatile storage device including: a first electrode; a second electrode; and a variable resistance layer which is sandwiched between the first electrode and the second electrode and in which a resistance value changes to two different resistance states, at least one of the first electrode and the second electrode is an electrode including a metallic nitride layer containing at least Ti and N, and a mole ratio (N/Ti ratio) between Ti and N in at least a part of the metallic nitride layer, the part being in contact with the variable resistance layer is 1.15 or more and a film density is 4.7 g/cc or more.Type: ApplicationFiled: April 19, 2012Publication date: October 4, 2012Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Eun-mi Kim, Yuichi Otani, Naomu Kitano
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Publication number: 20120199919Abstract: A gate electrode achieves a desired work function in a semiconductor device including a field-effect transistor equipped with a gate electrode composed of a metal nitride layer. The semiconductor device includes a silicon substrate and a field-effect transistor provided on the silicon substrate and having a gate insulating film and a gate electrode provided on the gate insulating film. The gate insulating film includes a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, and the gate electrode includes at least a metal nitride layer containing Ti and N. At least a part which is in contact with the gate insulating film of the metal nitride layer has a molar ratio between Ti and N (N/Ti ratio) of not less than 1.15 and a film density of not less than 4.7 g/cc.Type: ApplicationFiled: July 29, 2010Publication date: August 9, 2012Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
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Patent number: 8232189Abstract: The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 0<Si/(Si+Al)?0.1, and subjecting the metal oxide having the amorphous structure to annealing treatment at a temperature of 1000° C. or more to form the metal oxide including a crystalline phase.Type: GrantFiled: December 21, 2010Date of Patent: July 31, 2012Assignee: Canon Anelva CorporationInventors: Junko Ono, Naomu Kitano, Takashi Nakagawa
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Publication number: 20120161322Abstract: The present invention provides an electronic component manufacturing method including a step of embedding a metal film. An embodiment of the present invention includes a first step of depositing a barrier layer containing titanium nitride on an object to be processed on which a concave part is formed and a second step of filling a low-melting-point metal directly on the barrier layer under a temperature condition allowing the low-melting-point metal to flow, by a PCM sputtering method while forming a magnetic field by a magnet unit including plural magnets which are arranged at grid points of a polygonal grid so as to have different polarities between the neighboring magnets.Type: ApplicationFiled: June 20, 2011Publication date: June 28, 2012Applicant: CANON ANELVA CORPORATIONInventors: Shunichi Wakayanagi, Takayuki Saito, Takuya Seino, Akira Matsuo, Koji Yamazaki, Eitaro Morimoto, Yohsuke Shibuya, Yu Sato, Naomu Kitano
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Patent number: 8178934Abstract: The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015?(B/(A+B+N))?0.095 and N/(A+B+N) has a range of 0.045?(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0<(O/A)<2.0, and having a noncrystalline structure; and a step of performing an annealing treatment at 700° C. or higher on the metallic oxynitride having a noncrystalline structure to form a metallic oxynitride including a crystalline phase with a cubical crystal incorporation percentage of 80% or higher.Type: GrantFiled: November 23, 2010Date of Patent: May 15, 2012Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Nakagawa, Toru Tatsumi
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Patent number: 8148275Abstract: A method for forming dielectric films including metal nitride silicate on a silicon substrate, comprises a first step of depositing a film containing metal and silicon on a silicon substrate in a non-oxidizing atmosphere using a sputtering method; a second step of forming a film containing nitrogen, metal and silicon by nitriding the film containing metal and silicon; and a third step of forming a metal nitride silicate film by oxidizing the film containing nitrogen, metal and silicon.Type: GrantFiled: December 18, 2008Date of Patent: April 3, 2012Assignees: Canon Kabushiki Kaisha, Canon Anelva CorporationInventors: Yusuke Fukuchi, Naomu Kitano
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Publication number: 20120043617Abstract: This invention provides a semiconductor device having a field effect transistor comprising agate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1<X1<1.8, and in the second metal nitride layer 8, the molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X2 is 1.Type: ApplicationFiled: April 28, 2010Publication date: February 23, 2012Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi