Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.

Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.

Abstract: An object of the present invention is to effectively reduce power consumption. A semiconductor device according to the present invention includes a first cache memory, a second cache memory whose power consumption is larger than that of the first cache memory, and a main memory whose power consumption is larger than that of the second cache memory. Capacity of each of the first and second cache memories is determined so that a total value of values obtained by adjusting current values of the first cache memory, the second cache memory, and the main memory in accordance with hit ratios of the memories becomes a predetermine current threshold or less.

Abstract: A semiconductor device including a bus master that receives a clock; a first bus slave that receives a first slave clock and has a first number of waits, and a second bus slave that receives a second slave clock and has a second number of waits, wherein the second number of waits is higher than the first number of waits, and wherein a phase difference between the clock and the first slave clock is higher than a phase difference between the clock and the second slave clock.

Abstract: The present invention provides a technique for further improving the processing efficiency in a semiconductor device that arbitrates data transfer between a plurality of bus masters and a plurality of bus slaves. A bus control circuit controls data transfer in an address bus and a data bus between a plurality of bus masters and a plurality of bus slaves. The bus control circuit obtains access information representing the bus slave that each of the bus masters accesses on the basis of address signals output from the bus masters. The bus control circuit obtains busy information representing whether or not each bus slave is in a busy state. In the case where the bus masters compete with each other when accessing a bus slave, the bus control circuit arbitrates access from each bus master to the bus slave that is not in a busy state in accordance with the priority set for each bus master on the basis of the access information and the busy information.

Abstract: The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves. A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.

Abstract: An object of the present invention is to effectively reduce power consumption. A semiconductor device according to the present invention includes a first cache memory, a second cache memory whose power consumption is larger than that of the first cache memory, and a main memory whose power consumption is larger than that of the second cache memory. Capacity of each of the first and second cache memories is determined so that a total value of values obtained by adjusting current values of the first cache memory, the second cache memory, and the main memory in accordance with hit ratios of the memories becomes a predetermine current threshold or less.

Abstract: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

Abstract: The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves. A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.

Abstract: The present invention provides a technique for further improving the processing efficiency in a semiconductor device that arbitrates data transfer between a plurality of bus masters and a plurality of bus slaves. A bus control circuit controls data transfer in an address bus and a data bus between a plurality of bus masters and a plurality of bus slaves. The bus control circuit obtains access information representing the bus slave that each of the bus masters accesses on the basis of address signals output from the bus masters. The bus control circuit obtains busy information representing whether or not each bus slave is in a busy state. In the case where the bus masters compete with each other when accessing a bus slave, the bus control circuit arbitrates access from each bus master to the bus slave that is not in a busy state in accordance with the priority set for each bus master on the basis of the access information and the busy information.

Abstract: Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus.

Abstract: Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus.

Abstract: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.