Abstract: It is an object of the present invention to provide a technique capable of reducing power consumption of a semiconductor device even when the semiconductor device operates at high speed. The semiconductor device includes a module for outputting a signal, a delay element, a first output circuit having an input and an output, a first external terminal connected to the output of the first output circuit and to be connected to a signal wiring, and a second external terminal. The input of the first output circuit receives the signal delayed by the delay element. The second external terminal receives the signal without passing through the delay element. The signal of the second external terminal is used to change the potential level of the signal wiring to be connected to the first external terminal before the first output circuit changes the potential of the first external terminal based on the delayed signal.

Abstract: It is an object of the present invention to provide a technique capable of reducing power consumption of a semiconductor device even when the semiconductor device operates at high speed. The semiconductor device includes a module for outputting a signal, a delay element, a first output circuit having an input and an output, a first external terminal connected to the output of the first output circuit and to be connected to a signal wiring, and a second external terminal. The input of the first output circuit receives the signal delayed by the delay element. The second external terminal receives the signal without passing through the delay element. The signal of the second external terminal is used to change the potential level of the signal wiring to be connected to the first external terminal before the first output circuit changes the potential of the first external terminal based on the delayed signal.

Abstract: It is possible to achieve monitoring of a processor element while suppressing the cost. A multiprocessor system 1 includes a bus mechanism including a storage unit 6 configured to store bus access information when a first processor element 2 has executed a process to be monitored, a requesting unit 7 configured to request a second processor element 3 to execute a monitoring process after the first processor element 2 has completed the execution of the process to be monitored, and a comparing unit 8 configured to compare bus access information regarding access of the first processor element 2 stored in the storage unit 6 with bus access information input from the second processor element 3 when the second processor element 3 has executed the monitoring process. The second processor element 3 executes the monitoring process in an idle time.

Abstract: It is possible to achieve monitoring of a processor element while suppressing the cost. A multiprocessor system 1 includes a bus mechanism including a storage unit 6 configured to store bus access information when a first processor element 2 has executed a process to be monitored, a requesting unit 7 configured to request a second processor element 3 to execute a monitoring process after the first processor element 2 has completed the execution of the process to be monitored, and a comparing unit 8 configured to compare bus access information regarding access of the first processor element 2 stored in the storage unit 6 with bus access information input from the second processor element 3 when the second processor element 3 has executed the monitoring process. The second processor element 3 executes the monitoring process in an idle time.