Patents by Inventor Naotaka Maruyama
Naotaka Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10949249Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: July 1, 2019Date of Patent: March 16, 2021Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Publication number: 20190324792Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventor: Naotaka MARUYAMA
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Patent number: 10387191Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: August 22, 2017Date of Patent: August 20, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naotaka Maruyama
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Publication number: 20170357536Abstract: A plurality of tasks are processed simultaneously in a plurality of CPUs. A task control circuit is connected to the plurality of CPUs, and when executing a system call signal instruction, each CPU transmits a system call signal to the task control circuit. Upon receipt of a system call signal from a CPU 0, the task control circuit 200 refers to a processor management register, identifies a RUN-task of the CPU 0, selects a READY-task that is to be executed next, switches process data of the RUN-task and process data of the READY-task, and updates processor management information.Type: ApplicationFiled: August 4, 2017Publication date: December 14, 2017Inventor: Naotaka MARUYAMA
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Publication number: 20170351541Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Inventor: Naotaka MARUYAMA
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Publication number: 20170329629Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.Type: ApplicationFiled: August 2, 2017Publication date: November 16, 2017Inventor: Naotaka MARUYAMA
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Patent number: 9766924Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: July 6, 2015Date of Patent: September 19, 2017Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Patent number: 9753779Abstract: A plurality of tasks are processed simultaneously in a plurality of CPUs. A task control circuit is connected to the plurality of CPUs, and when executing a system call signal instruction, each CPU transmits a system call signal to the task control circuit. Upon receipt of a system call signal from a CPU 0, the task control circuit 200 refers to a processor management register, identifies a RUN-task of the CPU 0, selects a READY-task that is to be executed next, switches process data of the RUN-task and process data of the READY-task, and updates processor management information.Type: GrantFiled: November 17, 2014Date of Patent: September 5, 2017Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Patent number: 9753729Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.Type: GrantFiled: April 14, 2016Date of Patent: September 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naotaka Maruyama
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Publication number: 20160232004Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventor: Naotaka MARUYAMA
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Patent number: 9342350Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.Type: GrantFiled: August 24, 2006Date of Patent: May 17, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naotaka Maruyama
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Publication number: 20150301856Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: ApplicationFiled: July 6, 2015Publication date: October 22, 2015Inventor: Naotaka MARUYAMA
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Patent number: 9104470Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: April 2, 2014Date of Patent: August 11, 2015Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Patent number: 9047120Abstract: A queue control circuit controls the placement and retrieval of a plurality of tasks in a plurality of types of virtual queues. State registers are associated with respective tasks. Each of the state registers stores a task priority order, a queue ID of a virtual queue, and the order of placement in the virtual queue. Upon receipt of a normal placement command ENQ_TL, the queue control circuit establishes, in the state register for the placed task, QID of the virtual queue as the destination of placement and an order value indicating the end of the queue. When a reverse placement command ENQ_TP is received, QID of the destination virtual queue and an order value indicating the start of the queue are established. When a retrieval command DEQ is received, QID is cleared in the destination virtual queue.Type: GrantFiled: December 21, 2011Date of Patent: June 2, 2015Assignee: KERNELON SILICON INC.Inventor: Naotaka Maruyama
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Patent number: 8996761Abstract: A queue control circuit controls the placement and retrieval of a plurality of tasks in a plurality of types of virtual queues. State registers are associated with respective tasks. Each of the state registers stores a task priority order, a queue ID of a virtual queue, and the order of placement in the virtual queue. Upon receipt of a normal placement command ENQ_TL, the queue control circuit establishes, in the state register for the placed task, QID of the virtual queue as the destination of placement and an order value indicating the end of the queue. When a reverse placement command ENQ_TP is received, QID of the destination virtual queue and an order value indicating the start of the queue are established. When a retrieval command DEQ is received, QID is cleared in the destination virtual queue.Type: GrantFiled: August 10, 2007Date of Patent: March 31, 2015Assignee: Kernelon Silicon Inc.Inventor: Naotaka Maruyama
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Publication number: 20150074676Abstract: A plurality of tasks are processed simultaneously in a plurality of CPUs. A task control circuit is connected to the plurality of CPUs, and when executing a system call signal instruction, each CPU transmits a system call signal to the task control circuit. Upon receipt of a system call signal from a CPU 0, the task control circuit 200 refers to a processor management register, identifies a RUN-task of the CPU 0, selects a READY-task that is to be executed next, switches process data of the RUN-task and process data of the READY-task, and updates processor management information.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventor: Naotaka MARUYAMA
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Publication number: 20140215488Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: ApplicationFiled: April 2, 2014Publication date: July 31, 2014Applicant: Kernelon Silicon Inc.Inventor: Naotaka Maruyama
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Patent number: 8776079Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: November 20, 2012Date of Patent: July 8, 2014Assignee: Kernelon Silicon Inc.Inventor: Naotaka Maruyama
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Publication number: 20130081055Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: ApplicationFiled: November 20, 2012Publication date: March 28, 2013Inventor: Naotaka Maruyama
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Patent number: 8341641Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: August 16, 2007Date of Patent: December 25, 2012Assignee: Kernelon Silicon Inc.Inventor: Naotaka Maruyama