Abstract: A device includes a processor configured to: classify arithmetic processing devices that executes tasks in parallel by distributing loads into arithmetic processing device groups; select a representative arithmetic processing device; notify the representative arithmetic processing device of identification information of other arithmetic processing devices of an arithmetic processing device group to which the representative arithmetic processing device belongs; instruct the representative arithmetic processing device to acquire information regarding tasks to be executed by the arithmetic processing devices of the arithmetic processing device group from a first task list, and to generate a second task list; notify each other arithmetic processing devices of identification information of the representative arithmetic processing device; and instruct each other arithmetic processing device to acquire information regarding tasks to be executed by the representative arithmetic processing device and each other arithm

Abstract: An information processing apparatus, includes a memory; and a first processor coupled to the memory and configured to: identify a maximum operating frequency of each of a plurality of second processors, when executing a plurality of processes to be subjected to parallel processing by the plurality of second processors, measure a load value representing a magnitude of a load of each of the plurality of processes, and determine, based on the identified maximum operating frequency of each of the plurality of second processors and the measured load value of each of the plurality of processes, a specific processor as an assignment destination of each of the plurality of processes from the plurality of second processors.

Abstract: An information processing apparatus, includes a memory; and a first processor coupled to the memory and configured to: identify a maximum operating frequency of each of a plurality of second processors, when executing a plurality of processes to be subjected to parallel processing by the plurality of second processors, measure a load value representing a magnitude of a load of each of the plurality of processes, and determine, based on the identified maximum operating frequency of each of the plurality of second processors and the measured load value of each of the plurality of processes, a specific processor as an assignment destination of each of the plurality of processes from the plurality of second processors.

Abstract: An arithmetic processor, having: an arithmetic logical operation unit configured to execute an instruction; and a cache unit including a cache memory configured to store a part of data in a first main memory and a part of data in a second main memory which has a wider band than the first main memory when at least a predetermined capacity of data having consecutive addresses is accessed, and a cache control unit configured to read data in the cache memory responding to a memory request issued by the arithmetic logical operation unit and respond to the memory request source, wherein a ratio of capacity of the data in the second main memory with respect to the data in the first main memory stored in the cache memory is limited to a predetermined ratio or less.

Abstract: An arithmetic processor, having: an arithmetic logical operation unit configured to execute an instruction; and a cache unit including a cache memory configured to store a part of data in a first main memory and a part of data in a second main memory which has a wider band than the first main memory when at least a predetermined capacity of data having consecutive addresses is accessed, and a cache control unit configured to read data in the cache memory responding to a memory request issued by the arithmetic logical operation unit and respond to the memory request source, wherein a ratio of capacity of the data in the second main memory with respect to the data in the first main memory stored in the cache memory is limited to a predetermined ratio or less.

Abstract: A specification unit specifies numbers of cores executing processing when a predetermined number of processings to be executed in parallel is allocated to cores by same amount by changing number of processings to be allocated within a range of numbers of cores capable of executing parallel processing. A determination unit determines number of cores with highest processing performance as the number of cores executing the parallel processing from among the specified numbers of cores.

Abstract: A data deployment determination apparatus includes a correlation information creation processor that creates correlation information in which addresses indicating areas in a first memory are correlated with frequency information on memory accesses for the respective addresses, from trace information on a memory access to the first memory, a time reduction calculation processor that calculates, for each of the addresses, time reduction in memory accesses to data stored in the first memory based on the correlation information when data stored in the first memory is stored in a second memory which is a memory having a larger bandwidth than the first memory, and a data deployment determination processor that determines that first data stored in the address of which the time reduction is larger than the time reduction corresponding to second data stored in the address is to be stored in the second memory in preference to the second data.

Abstract: An information processing device includes a processor. The processor obtains, for every prescribed number of accesses to the memory, access history information representing a history of an access to a memory and information of an access time taken to obtain information from the memory through the access, and performs an interpolation process on access history information for the prescribed number of accesses on the basis of the access history information corresponding to the access time when the access time is shorter than a threshold.

Abstract: A node includes a sending unit that sends a signal to another node; a receiving unit that receives a signal from another node; a determining unit that determines, when the sending unit sends a signal to the other node, that synchronization has been established with the other node, that determines, when the receiving unit receives a signal from another node, that synchronization has been established with the other node, and that determines, when a node in which synchronization has already been established with the other two nodes in each of which synchronization has been established, that synchronization has been established with the nodes; and a selecting unit that selects an information processing apparatus that is not determined, by the determining unit, that synchronization has been established as the other node at the sending destination for the signal.

Abstract: A data deployment determination apparatus includes a correlation information creation processor that creates correlation information in which addresses indicating areas in a first memory are correlated with frequency information on memory accesses for the respective addresses, from trace information on a memory access to the first memory, a time reduction calculation processor that calculates, for each of the addresses, time reduction in memory accesses to data stored in the first memory based on the correlation information when data stored in the first memory is stored in a second memory which is a memory having a larger bandwidth than the first memory, and a data deployment determination processor that determines that first data stored in the address of which the time reduction is larger than the time reduction corresponding to second data stored in the address is to be stored in the second memory in preference to the second data.

Abstract: A node includes a sending unit that sends a signal to another node; a receiving unit that receives a signal from another node; a determining unit that determines, when the sending unit sends a signal to the other node, that synchronization has been established with the other node, that determines, when the receiving unit receives a signal from another node, that synchronization has been established with the other node, and that determines, when a node in which synchronization has already been established with the other two nodes in each of which synchronization has been established, that synchronization has been established with the nodes; and a selecting unit that selects an information processing apparatus that is not determined, by the determining unit, that synchronization has been established as the other node at the sending destination for the signal.

Abstract: A specification unit specifies numbers of cores executing processing when a predetermined number of processings to be executed in parallel is allocated to cores by same amount by changing number of processings to be allocated within a range of numbers of cores capable of executing parallel processing. A determination unit determines number of cores with highest processing performance as the number of cores executing the parallel processing from among the specified numbers of cores.