Abstract: A signal regeneration circuit using first and second phase-locked loop (PLL) circuits each having a phase comparator, a loop filter and a voltage controlled oscillator (VCO) in which the phase of an input signal is shifted by a desired amount. The first PLL operates as an input signal frequency averaging means, and the second PLL operates to satisfy the final performance as a signal regenerative circuit based on the output of the VCO in the first PLL, thereby producing as a regenerative signal the output of the VCO in the second PLL. Thus, this signal regeneration circuit can regenerate a clear signal having no noise from an unclear input signal deeply immersed in noise.