Patents by Inventor Naoto Iga

Naoto Iga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8718082
    Abstract: In a network system of this invention including a plurality of network devices that transfer frames by repeating, in a constant cycle, a reserved transfer interval that is a time band, in which a frame is transferred with a reservation and a free transfer interval that is a time band, in which a frame is freely transferred, a relay network device that links a first network device that is a transmission source of a frame and a second network device that is a transmission destination of the frame and the first network device execute a reservation processing such that the same time band within the reserved transfer interval is reserved and transfer the frame from the first network device to the second network device on the basis of the reservation result.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: May 6, 2014
    Assignees: Toyota Jidosha Kabushiki Kaisha, Renesas Electronics Corporation
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
  • Patent number: 8385357
    Abstract: A network device of is a network device that transfers frames by repeating, in a constant cycle, a reserved transfer interval and a free transfer interval. The network device includes a transmission port, a cycle timer, a mode switching control unit that monitors a transfer state of the transmission port and selects a store-and-forward system when the transmission port is in the transfer process and selects a cut-through system when the transmission port is not in the transfer process, and a transfer prohibition control unit that selects the cut-through system as a transfer system when a non-reserved frame is transmitted and switches a transfer method of the non-reserved frame to the store-and-forward system when a reserved transfer interval is established, with reference to the cycle timer.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: February 26, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
  • Publication number: 20110072145
    Abstract: A network device that transfers frames by repeating, in a constant cycle, a reserved transfer interval that is a time band, in which a frame is transferred with a reservation, and a free transfer interval that is a time band, in which a frame is freely transferred, includes: a BPDU generation unit that generates a first BPDU; and a BPDU transmission instruction unit that instructs to arrange the first BPDU in the reserved transfer interval and transmit the first BPDU to a first other network device.
    Type: Application
    Filed: March 26, 2009
    Publication date: March 24, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA.
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
  • Publication number: 20110051751
    Abstract: In a network system of this invention including a plurality of network devices that transfer frames by repeating, in a constant cycle, a reserved transfer interval that is a time band, in which a frame is transferred with a reservation and a free transfer interval that is a time band, in which a frame is freely transferred, a relay network device that links a first network device that is a transmission source of a frame and a second network device that is a transmission destination of the frame and the first network device execute a reservation processing such that the same time band within the reserved transfer interval is reserved and transfer the frame from the first network device to the second network device on the basis of the reservation result.
    Type: Application
    Filed: March 26, 2009
    Publication date: March 3, 2011
    Applicants: Toyota Jidosha Kabushiki Kaisha, Renesas Electronics Corporation
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
  • Publication number: 20110026654
    Abstract: A network device that arranges and transfers in an initial period of a cycle a synchronization frame that synchronizes network devices within a network includes: a cycle timer that measures a time within the cycle and a synchronization management unit that suspends frame transmission for a predetermined period till a start of the next cycle in each cycle, on the basis of information from a cycle timer.
    Type: Application
    Filed: March 25, 2009
    Publication date: February 3, 2011
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, Renesas Electronics Corporation
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Ilyama
  • Publication number: 20110026538
    Abstract: A network device of is a network device that transfers frames by repeating, in a constant cycle, a reserved transfer interval and a free transfer interval. The network device includes a transmission port, a cycle timer, a mode switching control unit that monitors a transfer state of the transmission port and selects a store-and-forward system when the transmission port is in the transfer process and selects a cut-through system when the transmission port is not in the transfer process, and a transfer prohibition control unit that selects the cut-through system as a transfer system when a non-reserved frame is transmitted and switches a transfer method of the non-reserved frame to the store-and-forward system when a reserved transfer interval is established, with reference to the cycle timer.
    Type: Application
    Filed: March 26, 2009
    Publication date: February 3, 2011
    Applicants: Toyota Jidosha Kabushiki Kaisha, Renesas Electronics Corporation
    Inventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
  • Patent number: 5570371
    Abstract: A J1 byte processing circuit is provided with a J1 byte latch pulse sampling circuit, which samples in preset periods a J1 byte latch pulse. The sampling circuit generates, in accordance with the sampled J1 byte latch pulse, a data acquisition request to instruct acquisition of a J1 byte from the path overhead of an SPE level signal of STS-1 with the J1 byte latch pulse sampled by the sampling circuit, and sends it to a microcomputer interface. The microcomputer acquires into it the J1 byte from the J1 latching section in accordance with the data acquisition request. This configuration reduces the processing load on the microcomputer, and thereby enables the microcomputer to execute other processes even during the collection of J1 bytes.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: October 29, 1996
    Assignee: NEC Corporation
    Inventor: Naoto Iga
  • Patent number: 5383189
    Abstract: The present invention provides a method and circuit for demultiplexing digital signals which generates no errors even when destuffing jitters are heavy. A buffer memory performs digital smoothing of the jitters which are periodically generated in lower order signals demultiplexed from higher order signals by a demultiplexing circuit. An analog IC performs resmoothing of the lower order signals which have been smoothed by the buffer memory, and thereafter performs digital/analog conversion thereof and outputs the lower order signals which have no jitters, through a transformer.
    Type: Grant
    Filed: March 13, 1992
    Date of Patent: January 17, 1995
    Assignee: NEC Corporation
    Inventors: Kazunori Matsuyama, Naoto Iga