Patents by Inventor Naoto KAGUCHI
Naoto KAGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220406893Abstract: An object is to provide a semiconductor device that implements cost reduction as well as determination of withstand voltage characteristics. A semiconductor substrate includes a semiconductor element on the front surface thereof and a back surface electrode on the back surface thereof that controls the operation of the semiconductor element. A first electrode and a second electrode are provided in a terminal region outside an active region in which the semiconductor element is formed. An insulating film is provided between the first electrode and the second electrode. The second electrode is provided on an insulating interlayer film provided on the front surface of the semiconductor substrate. The first electrode is in contact with the front surface of the semiconductor substrate and is provided on the semiconductor substrate closer to an end portion thereof than the second electrode is, and is electrically connected to the back surface electrode.Type: ApplicationFiled: December 23, 2019Publication date: December 22, 2022Applicant: Mitsubishi Electric CorporationInventor: Naoto KAGUCHI
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Patent number: 10998436Abstract: A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.Type: GrantFiled: March 16, 2017Date of Patent: May 4, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Jun Fujita, Naoto Kaguchi, Fumio Wada
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Patent number: 10802047Abstract: An inspection device according to the invention of the present application includes a fixing plate, plural expanding and contracting portions whose one ends are fixed to the fixing plate, plural contact probes that are fixed to the other ends of the plural expanding and contracting portions respectively, and plural fixing portions which are provided to the plural contact probes respectively, wherein each fixing portion performs switching between a fixing state where an upper end of a corresponding contact probe is fixed at a first position and a releasing state where the contact probe is not fixed, the contact probe is pulled to the fixing plate by a corresponding expanding and contracting portion under the fixing state, and the upper end of the contact probe is placed at a second position closer to the fixing plate than the first position under the releasing state.Type: GrantFiled: October 26, 2016Date of Patent: October 13, 2020Assignee: Mitsubishi Electric CorporationInventors: Naoto Kaguchi, Yuji Ebiike
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Publication number: 20200141977Abstract: An inspection device according to the invention of the present application includes a fixing plate, plural expanding and contracting portions whose one ends are fixed to the fixing plate, plural contact probes that are fixed to the other ends of the plural expanding and contracting portions respectively, and plural fixing portions which are provided to the plural contact probes respectively, wherein each fixing portion performs switching between a fixing state where an upper end of a corresponding contact probe is fixed at a first position and a releasing state where the contact probe is not fixed, the contact probe is pulled to the fixing plate by a corresponding expanding and contracting portion under the fixing state, and the upper end of the contact probe is placed at a second position closer to the fixing plate than the first position under the releasing state.Type: ApplicationFiled: October 26, 2016Publication date: May 7, 2020Applicant: Mitsubishi Electric CorporationInventors: Naoto KAGUCHI, Yuji EBIIKE
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Publication number: 20190393333Abstract: A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.Type: ApplicationFiled: March 16, 2017Publication date: December 26, 2019Applicant: Mitsubishi Electric CorporationInventors: Jun FUJITA, Naoto KAGUCHI, Fumio WADA
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Patent number: 9627383Abstract: A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.Type: GrantFiled: September 17, 2013Date of Patent: April 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoto Kaguchi, Eisuke Suekawa, Masaaki Ikegami
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Patent number: 9627571Abstract: An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.Type: GrantFiled: March 24, 2014Date of Patent: April 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoto Kaguchi, Yoichiro Tarui
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Patent number: 9472543Abstract: The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a n+ source layer to sandwich a field insulating film, a second gate electrode being the same layer as a gate polysilicon and formed at least on the field insulating film, a third gate electrode formed on one of portions of the second source layer to be electrically connected to the second gate electrode, and a second source electrode formed on the other portion of the second source layer.Type: GrantFiled: March 24, 2014Date of Patent: October 18, 2016Assignee: Mitsubishi Electric CorporationInventors: Eisuke Suekawa, Naoto Kaguchi, Masaaki Ikegami
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Publication number: 20160163703Abstract: A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.Type: ApplicationFiled: September 17, 2013Publication date: June 9, 2016Applicant: Mitsubishi Electric CorporationInventors: Naoto KAGUCHI, Eisuke SUEKAWA, Masaaki IKEGAMI
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Publication number: 20150014705Abstract: An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.Type: ApplicationFiled: March 24, 2014Publication date: January 15, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naoto KAGUCHI, Yoichiro TARUI
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Patent number: 8932944Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.Type: GrantFiled: July 24, 2013Date of Patent: January 13, 2015Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Naoto Kaguchi, Takuyo Nakamura
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Publication number: 20150008450Abstract: The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a n+ source layer to sandwich a field insulating film, a second gate electrode being the same layer as a gate polysilicon and formed at least on the field insulating film, a third gate electrode formed on one of portions of the second source layer to be electrically connected to the second gate electrode, and a second source electrode formed on the other portion of the second source layer.Type: ApplicationFiled: March 24, 2014Publication date: January 8, 2015Applicant: Mitsubishi Electric CorporationInventors: Eisuke SUEKAWA, Naoto KAGUCHI, Masaaki IKEGAMI
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Patent number: 8860451Abstract: A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.Type: GrantFiled: February 8, 2012Date of Patent: October 14, 2014Assignee: Mitshubishi Electronic CorporationInventors: Naoto Kaguchi, Masaaki Ikegami
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Patent number: 8692244Abstract: A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.Type: GrantFiled: June 30, 2011Date of Patent: April 8, 2014Assignee: Mitsubishi Electric CorporationInventors: Naoto Kaguchi, Norihisa Asano, Katsumi Sato
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Publication number: 20130309851Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: Mitsubishi Electric CorporationInventors: Yoichiro TARUI, Naoto Kaguchi, Takuyo Nakamura
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Patent number: 8525189Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.Type: GrantFiled: October 4, 2011Date of Patent: September 3, 2013Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Naoto Kaguchi, Takuyo Nakamura
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Publication number: 20120299613Abstract: A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.Type: ApplicationFiled: February 8, 2012Publication date: November 29, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naoto KAGUCHI, Masaaki IKEGAMI
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Publication number: 20120132924Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.Type: ApplicationFiled: October 4, 2011Publication date: May 31, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro TARUI, Naoto Kaguchi, Takuyo Nakamura
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Publication number: 20120104415Abstract: A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.Type: ApplicationFiled: June 30, 2011Publication date: May 3, 2012Applicant: MITSUBISHI ELECTRONIC CORPORATIONInventors: Naoto KAGUCHI, Norihisa ASANO, Katsumi SATO