Patents by Inventor Naoto Niisoe
Naoto Niisoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110278689Abstract: A solid-state imaging device includes an n-type semiconductor substrate 203, a p-type well 204 provided in the substrate 203, photodiodes 201 arranged in a matrix above the substrate 203, and isolation regions 202 corresponding to the photodiodes 201. The isolation regions 202 each include a p-type first impurity diffusion layer 208. On a part of the p-type well 204 corresponding to the photodiode 201, an n-type first impurity diffusion layer 206 and a p-type impurity diffusion layer 207 that are to be formed as a light receiving part. Only immediately below the photodiode 201 corresponding to red pixels, an n-type second impurity diffusion layer 205 is provided. Immediately below the photodiode 201 corresponding to blue and green pixels, a p-type second impurity diffusion layer 209 is provided.Type: ApplicationFiled: March 22, 2011Publication date: November 17, 2011Inventor: Naoto NIISOE
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Patent number: 7964451Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).Type: GrantFiled: December 6, 2006Date of Patent: June 21, 2011Assignee: Panasonic CorporationInventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
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Patent number: 7585691Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.Type: GrantFiled: April 28, 2008Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
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Publication number: 20090194795Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).Type: ApplicationFiled: December 6, 2006Publication date: August 6, 2009Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
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Publication number: 20090045442Abstract: A first oxide film (102) and a first nitride film (103) are formed over a semiconductor substrate (101) so as to be stacked in this order. A plurality of first gate electrodes (104) are arranged on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. Upper part and side walls of each of the first gate electrode (104) is covered by a second oxide film (105). The second oxide film (105) and part of the first nitride film (103) located between the first gate electrodes (104) are covered by the second nitride film (106). A plurality of second gate electrodes (107) are formed on at least part of the second nitride film (106) located between adjacent two of the first gate electrodes (104).Type: ApplicationFiled: December 6, 2006Publication date: February 19, 2009Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
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Publication number: 20080213939Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.Type: ApplicationFiled: April 28, 2008Publication date: September 4, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
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Patent number: 7323758Abstract: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high melting point metal compound film having a light shielding property or an insulating film having a light transmissive property. Thus, the scattering ratio of the incident light at the surface of the light shielding film 7 can be uniform among all the pixels, and as a result, a solid state imaging device having suppressed sensitivity non-uniformity can be realized. Since the surface of the light shielding film 7 is not oxidized, the thickness of the light shielding film 7 can be reduced. Thus, the present invention can comply with the demand for size reduction of the pixels.Type: GrantFiled: March 16, 2005Date of Patent: January 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoto Niisoe, Hiroe Ogata, Rieko Nishio, Toshihiko Yano, Hitoshi Doi
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Publication number: 20060081848Abstract: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high melting point metal compound film having a light shielding property or an insulating film having a light transmissive property. Thus, the scattering ratio of the incident light at the surface of the light shielding film 7 can be uniform among all the pixels, and as a result, a solid state imaging device having suppressed sensitivity non-uniformity can be realized. Since the surface of the light shielding film 7 is not oxidized, the thickness of the light shielding film 7 can be reduced. Thus, the present invention can comply with the demand for size reduction of the pixels.Type: ApplicationFiled: March 16, 2005Publication date: April 20, 2006Inventors: Naoto Niisoe, Hiroe Ogata, Rieko Nishio, Toshihiko Yano, Hitoshi Doi
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Patent number: 7005364Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.Type: GrantFiled: December 29, 2003Date of Patent: February 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Naoto Niisoe
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Publication number: 20050181522Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.Type: ApplicationFiled: January 10, 2005Publication date: August 18, 2005Inventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
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Publication number: 20050095824Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.Type: ApplicationFiled: December 29, 2003Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Naoto Niisoe
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Patent number: 6002145Abstract: A solid-state imaging device comprises photodiodes arranged in columns on a light receiving region, and CCDs arranged in alternations with the columns of the photodiodes; wherein, when charges are stored, a potential barrier of an isolation area between CCDs formed between the photodiodes and the CCDs is formed higher with respect to signal charges than a potential barrier of an isolation area between photodiodes formed between the photodiodes. By this solid-state imaging device, signal charges generated by the incident light on this isolation area between photodiodes can appropriately be stored in the photodiodes. Therefore, it is not necessary to form a metal shielding film on the isolation area between photodiodes, and the efficient area of the photodiodes is increased by taking the area of the photodiodes at maximum. Thus, high sensitivity is obtained.Type: GrantFiled: February 24, 1998Date of Patent: December 14, 1999Assignee: Matsushita Electronics CorporationInventor: Naoto Niisoe