Patents by Inventor Naoto Niisoe

Naoto Niisoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110278689
    Abstract: A solid-state imaging device includes an n-type semiconductor substrate 203, a p-type well 204 provided in the substrate 203, photodiodes 201 arranged in a matrix above the substrate 203, and isolation regions 202 corresponding to the photodiodes 201. The isolation regions 202 each include a p-type first impurity diffusion layer 208. On a part of the p-type well 204 corresponding to the photodiode 201, an n-type first impurity diffusion layer 206 and a p-type impurity diffusion layer 207 that are to be formed as a light receiving part. Only immediately below the photodiode 201 corresponding to red pixels, an n-type second impurity diffusion layer 205 is provided. Immediately below the photodiode 201 corresponding to blue and green pixels, a p-type second impurity diffusion layer 209 is provided.
    Type: Application
    Filed: March 22, 2011
    Publication date: November 17, 2011
    Inventor: Naoto NIISOE
  • Patent number: 7964451
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Patent number: 7585691
    Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
  • Publication number: 20090194795
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Application
    Filed: December 6, 2006
    Publication date: August 6, 2009
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Publication number: 20090045442
    Abstract: A first oxide film (102) and a first nitride film (103) are formed over a semiconductor substrate (101) so as to be stacked in this order. A plurality of first gate electrodes (104) are arranged on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. Upper part and side walls of each of the first gate electrode (104) is covered by a second oxide film (105). The second oxide film (105) and part of the first nitride film (103) located between the first gate electrodes (104) are covered by the second nitride film (106). A plurality of second gate electrodes (107) are formed on at least part of the second nitride film (106) located between adjacent two of the first gate electrodes (104).
    Type: Application
    Filed: December 6, 2006
    Publication date: February 19, 2009
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Publication number: 20080213939
    Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.
    Type: Application
    Filed: April 28, 2008
    Publication date: September 4, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
  • Patent number: 7323758
    Abstract: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high melting point metal compound film having a light shielding property or an insulating film having a light transmissive property. Thus, the scattering ratio of the incident light at the surface of the light shielding film 7 can be uniform among all the pixels, and as a result, a solid state imaging device having suppressed sensitivity non-uniformity can be realized. Since the surface of the light shielding film 7 is not oxidized, the thickness of the light shielding film 7 can be reduced. Thus, the present invention can comply with the demand for size reduction of the pixels.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoto Niisoe, Hiroe Ogata, Rieko Nishio, Toshihiko Yano, Hitoshi Doi
  • Publication number: 20060081848
    Abstract: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high melting point metal compound film having a light shielding property or an insulating film having a light transmissive property. Thus, the scattering ratio of the incident light at the surface of the light shielding film 7 can be uniform among all the pixels, and as a result, a solid state imaging device having suppressed sensitivity non-uniformity can be realized. Since the surface of the light shielding film 7 is not oxidized, the thickness of the light shielding film 7 can be reduced. Thus, the present invention can comply with the demand for size reduction of the pixels.
    Type: Application
    Filed: March 16, 2005
    Publication date: April 20, 2006
    Inventors: Naoto Niisoe, Hiroe Ogata, Rieko Nishio, Toshihiko Yano, Hitoshi Doi
  • Patent number: 7005364
    Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoto Niisoe
  • Publication number: 20050181522
    Abstract: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon film 13, the surface of the light-shielding film may be covered with any one of a high melting point metal film containing silicon, a high melting point metal silicide film and an oxide film. Thus, the adherence between the light-shielding film 10a and the resist can be increased and the resist can be prevented from being peeled from the light-shielding film, and thus a solid-state imaging device with a high yield even with small pixels and a method for producing the same can be provided.
    Type: Application
    Filed: January 10, 2005
    Publication date: August 18, 2005
    Inventors: Toshihiko Yano, Hitoshi Doi, Naoto Niisoe
  • Publication number: 20050095824
    Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.
    Type: Application
    Filed: December 29, 2003
    Publication date: May 5, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Naoto Niisoe
  • Patent number: 6002145
    Abstract: A solid-state imaging device comprises photodiodes arranged in columns on a light receiving region, and CCDs arranged in alternations with the columns of the photodiodes; wherein, when charges are stored, a potential barrier of an isolation area between CCDs formed between the photodiodes and the CCDs is formed higher with respect to signal charges than a potential barrier of an isolation area between photodiodes formed between the photodiodes. By this solid-state imaging device, signal charges generated by the incident light on this isolation area between photodiodes can appropriately be stored in the photodiodes. Therefore, it is not necessary to form a metal shielding film on the isolation area between photodiodes, and the efficient area of the photodiodes is increased by taking the area of the photodiodes at maximum. Thus, high sensitivity is obtained.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: December 14, 1999
    Assignee: Matsushita Electronics Corporation
    Inventor: Naoto Niisoe