Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.

Abstract: A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

Abstract: A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.

Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.

Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.