Abstract: Provided is a route search device and a non-transitory computer-readable medium that can search a route where a transportation means more suitable for a user is selected. When searching a route to a destination, a change point at which the transportation means is changed is set, and then the priority in selecting a transportation means for moving in a section from a plurality kinds of transportation means is set based on at least one of an attribute of a start point and an attribute of an end point in the section for each section where a distance between a departure place and a destination is divided at the change point to search the route to the destination using the transportation means selected for each of the plurality of sections based on the set priority.

Abstract: An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Abstract: A wide high concentration P+ type region is formed on the surface of an N− type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P+ type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: A concave channel type DMOS structure having an improved gate-to-source breakdown voltage are disclosed. By establishing a curvature at a corner portion of a lattice-like pattern in a groove portion for forming the concave channel structure, the shape of the tip of a three-dimensionally projecting portion of a semiconductor region determined by a plane angle of the corner portion in the lattice-like pattern and an inclination of the groove portion is rounded. That is, a three-dimensionally sharpened corner portion in the concave channel structure is rounded, and thereby electric field concentration at the corner portion is suppressed.

Abstract: A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

Abstract: An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

Abstract: A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n.sup.+ type region, the impurity concentration of which is caused to be 1.times.10.sup.19 cm.sup.-3 or more, is formed in an n.sup.- type semiconductor layer. By means of this, defects occur within the n.sup.+ type region or in a proximity of the boundary of the n.sup.+ type region and the n.sup.- type semiconductor layer. The defects trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.

Abstract: A semiconductor device has an electrode interposed between an interlayer insulation film and a wire which is bonded thereto. A main component of the electrode is aluminum and the electrode contains fine-grained silicon in a concentration of 0.1 to 0.6 weight %. As a result, even if large ultrasonic power, a large load or the like is applied to the electrode when the wire is wire-bonded, damage such as the formation of a crack hardly generates at the interlayer insulation film. Therefore, the occurrence of defects due to the wire-bonding can be reduced.

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area.

Abstract: The insulated gate bipolar transistor (IGBT) integrates the anti-excess voltage protection function and a drain voltage fixing function. When a voltage is applied across the drain electrode and the source electrode of the IGBT, a depletion zone propagates from a p-n junction between a p base layer and a n.sup.- drain layer toward inside of the n.sup.- drain layer. A critical electric field is also established, causing generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.- drain layer. Conduction exist between the drain electrode and the source electrode, at an applied voltage lower than a drain-source voltage at which the depletion region reaches a p.sup.+ drain layer through the n.sup.- drain layer, the applied voltage being equal to or lower than a critical voltage that causes generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.

Abstract: Arsenic is diffused previously on a most outside surface of a n.sup.- -type epitaxial layer (2), and after forming gate oxide films (3) and gate electrodes (4), p-type base regions (8) and n.sup.+ -type source layers (7) are formed in a self-aligned manner with the gate electrodes (4) by a DSA technique and double diffusion. Thereby, a lateral directional junction depth of the p-type base regions (8) is compensated at the most outside surface, and a channel length of channels (9) is shortened substantially. When designing a threshold voltage, an impurity density of the p-type base regions (8) can be set higher than that of the conventional device by an amount corresponding to an impurity density of the arsenic of the most outside surface, and p-type pinch layers (14) formed underneath the n.sup.+ -type source layers (7) of the p-type base regions are (8) are lowered correspondingly in resistance.

Abstract: An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers.

Abstract: An IGBT chip includes a unit cell region and a guard ring region which surrounds the unit cell region. In the unit cell region, a plurality of IGBT unit cells are formed, each of which comprises a base layer, a source layer, a common gate electrode, a common source electrode, and a common drain electrode. In the guard ring region, at least one diffused layer making up a guard ring is formed. Further, an annular diffused layer is formed and is connected to the drain electrode. The annular diffused layer is disposed away from the outermost guard ring by a specified length. This length is such that the punch-through occurs before the avalanche breakdown voltage of the junction associated with the outermost guard ring. Therefore, the withstand voltage against the avalanche breakdown when surge voltage is applied to the drain electrode is improved.

Abstract: A semiconductor device has a protective Zener diode formed through an insulation film to a silicon substrate having a power MOSFET formed thereon. The breakdown strength of the insulation film is substantially improved and the withstand voltage of the Zener diode can be set to a high value. A gate plate 11 electrically connected to an outer circumferential part of a p-type diffusion region 104 is installed, and element parts 112a-112c and equipotential plates 113a-133c constituting a Zener diode group 115 are formed. The equipotential plates 113a-133c hold a prescribed potential by Zener diode pairs 114 of the element parts 112a-112c.

Abstract: A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.

Abstract: An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode.

Abstract: A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.

Abstract: This invention is basically related to an insulated gate bipolar transistor comprising a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the substrate and having a low concentration of impurities, a first conductivity type base layer formed on a surface of the semiconductor layer, a second conductivity type source layer formed on the surface of the base layer and having a channel region at at least one end thereof, a gate electrode, a source electrode and a drain electrode, and is characterized in that a voltage dropping portion is provided either inside the source layer or between the source layer and the source electrode. Accordingly an insulated gate bipolar semiconductor transistor having this configuration can prevent a latch up phenomenon caused by a voltage drop in a source layer.