Patents by Inventor Naoto Shiino

Naoto Shiino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10509700
    Abstract: A storage system has a storage controller and a RAID group. The storage controller has policy management information such that one failure recovery process among a plurality of differing failure recovery processes is associated with each RAID group, and when an error in a command issued to a RAID group is detected, the failure recovery process associated with the RAID group to which the command was issued is specified on the basis of the policy management information, and the specified failure recovery process is executed.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 17, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Honda, Naoto Shiino, Toru Ando, Keiichiro Uchida
  • Publication number: 20180196718
    Abstract: A storage system has a storage controller and a RAID group. The storage controller has policy management information such that one failure recovery process among a plurality of differing failure recovery processes is associated with each RAID group, and when an error in a command issued to a RAID group is detected, the failure recovery process associated with the RAID group to which the command was issued is specified on the basis of the policy management information, and the specified failure recovery process is executed.
    Type: Application
    Filed: November 10, 2015
    Publication date: July 12, 2018
    Inventors: Kiyoshi HONDA, Naoto SHIINO, Toru ANDO, Keiichiro UCHIDA
  • Patent number: 9086807
    Abstract: A storage apparatus and tier control method capable of executing hierarchical control based on variable performance of SSDs are suggested. With a storage apparatus equipped with a plurality of drives composed of flash memories, the storage apparatus includes a controller for hierarchically controlling storage areas provided by the plurality of drives by classifying the storage areas into a plurality of tiers with different performances and managing them, wherein the controller: decides a first tier, to which each of the drives should belong, based on performance of the drive; decides to change the tier, to which the drive should belong, from the first tier to a second tier different from the first tier based on the drive's performance, which varies depending on property of the drive; and changes the tier, to which the drive determined to change its tier should belong, from the first tier to the second tier.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 21, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Gosuke Okada, Takashi Chikusa, Keiichiro Uchida, Megumi Hokazono, Naoto Shiino, Mamoru Motonaga
  • Publication number: 20150160858
    Abstract: A storage apparatus and tier control method capable of executing hierarchical control based on variable performance of SSDs are suggested. With a storage apparatus equipped with a plurality of drives composed of flash memories, the storage apparatus includes a controller for hierarchically controlling storage areas provided by the plurality of drives by classifying the storage areas into a plurality of tiers with different performances and managing them, wherein the controller: decides a first tier, to which each of the drives should belong, based on performance of the drive; decides to change the tier, to which the drive should belong, from the first tier to a second tier different from the first tier based on the drive's performance, which varies depending on property of the drive; and changes the tier, to which the drive determined to change its tier should belong, from the first tier to the second tier.
    Type: Application
    Filed: August 26, 2013
    Publication date: June 11, 2015
    Inventors: Gosuke Okada, Takashi Chikusa, Keiichiro Uchida, Megumi Hokazono, Naoto Shiino, Mamoru Motonaga
  • Patent number: 8489937
    Abstract: In storage subsystems, due to the significant increase in HDD capacity, the time for executing online verification is elongated, affecting accesses from the host computer. By comprehending the status of accesses to the HDD, the sections where error has occurred and the status of restoration thereof, it becomes possible to detect defective or error sections efficiently at an early stage, according to which the reliability and access performance of the storage subsystem can be improved. The present storage subsystem executes one or more of the following processes: (M1) intensive verification of a circumference of an error LBA, (M2) an area-based prioritized verification, and (M3) continuous verification performed for a long period of time to (V1) an area in which error has occurred via IO access, (V2) a highly accessed area, and (V3) during a period of time when IO access is low.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Gosuke Okada, Takashi Yamazaki, Mamoru Motonaga, Naoto Shiino, Takashi Nozawa, Megumi Hokazono
  • Publication number: 20130145223
    Abstract: In storage subsystems, due to the significant increase in HDD capacity, the time for executing online verification is elongated, affecting accesses from the host computer. By comprehending the status of accesses to the HDD, the sections where error has occurred and the status of restoration thereof, it becomes possible to detect defective or error sections efficiently at an early stage, according to which the reliability and access performance of the storage subsystem can be improved. The present storage subsystem executes one or more of the following processes: (M1) intensive verification of a circumference of an error LBA, (M2) an area-based prioritized verification, and (M3) continuous verification performed for a long period of time to (V1) an area in which error has occurred via IO access, (V2) a highly accessed area, and (V3) during a period of time when IO access is low.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Inventors: Gosuke Okada, Takashi Yamazaki, Mamoru Motonaga, Naoto Shiino, Takashi Nozawa, Megumi Hokazono
  • Patent number: 8180952
    Abstract: A system according to the invention reads/writes data by using a memory device performing a wear leveling. A host 4 reads/writes data from/in a flash memory device 2. A first protection code BC is added to the end of a logical block for every logical block of 512 bytes. A second protection code FC is added to the head of the logical blocks. The first protection code BC and the second protection code FC are configured to include data for specifying the logical address. When data is read from the flash memory device 2, the logical address obtained from the first protection code BC is compared to the logical address obtained from the second protection code. When both logical addresses are identical, it is determined that correct data is read.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 15, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yukiyoshi Takamura, Naoto Shiino
  • Publication number: 20100057978
    Abstract: A system according to the invention reads/writes data by using a memory device performing a wear leveling. A host 4 reads/writes data from/in a flash memory device 2. A first protection code BC is added to the end of a logical block for every logical block of 512 bytes. A second protection code FC is added to the head of the logical blocks. The first protection code BC and the second protection code FC are configured to include data for specifying the logical address. When data is read from the flash memory device 2, the logical address obtained from the first protection code BC is compared to the logical address obtained from the second protection code. When both logical addresses are identical, it is determined that correct data is read.
    Type: Application
    Filed: October 20, 2008
    Publication date: March 4, 2010
    Inventors: Yukiyoshi Takamura, Naoto Shiino