Patents by Inventor Naoto Sugai

Naoto Sugai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200290249
    Abstract: The present invention relates to a waterproof component that is an insert molded body formed from a thermoplastic resin composition and a metal component, wherein the thermoplastic resin composition contains a thermoplastic resin (A) and an inorganic fibrous reinforcement (B); the content of the inorganic fibrous reinforcement (B) is 8 to 130 parts by mass based on 100 parts by mass of the thermoplastic resin (A); and the inorganic fibrous reinforcement (B) has an average fiber diameter of 10 ?m or less and an average fiber length of 300 ?m or less.
    Type: Application
    Filed: October 26, 2018
    Publication date: September 17, 2020
    Applicant: KURARAY CO., LTD.
    Inventors: Naoto SUGAI, Yuki ITO, Takaharu SHIGEMATSU
  • Patent number: 8051234
    Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Takata, Naoto Sugai
  • Publication number: 20110022759
    Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
    Type: Application
    Filed: August 31, 2010
    Publication date: January 27, 2011
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hirokazu TAKATA, Naoto Sugai
  • Patent number: 7805555
    Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: September 28, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hirokazu Takata, Naoto Sugai
  • Publication number: 20080172511
    Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 17, 2008
    Inventors: Hirokazu Takata, Naoto Sugai
  • Patent number: 6795890
    Abstract: A data processing device includes flash memory; nonvolatile memory having an erasure block buffer in which there are stored data recorded in an erasure-unit region of the flash memory; a write control controller for writing into the erasure block buffer write request data, which are to be written into the flash memory; a save unit for saving non-changing data stored in the flash memory to the erasure block buffer; an erasure instruction unit for instructing erasure of the data from the flash memory; and a write unit for writing the data recorded in the erasure block buffer to the flash memory.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: September 21, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoto Sugai, Atsushi Settsu, Saburo Kobayashi
  • Patent number: 6571312
    Abstract: A data processing device includes flash memory 101; nonvolatile memory 102 having an erasure block buffer 103 in which there are stored data recorded in an erasure-unit region of the flash memory 101; a write controller 111 for writing into the erasure block buffer 103 write request data which are to be written into the flash memory 101; a save unit 112 for saving non-changing data stored in the flash memory 101 to the erasure block buffer 103; an erasure instruction unit 301 for instructing erasure of the data from the erasure-unit region of flash memory 101; and a write unit for writing the data recorded in the erasure block buffer 103 to the flash memory 101. A comparison may be made between the erasure unit regions into which first and second write data are to be written. The data processing device may further include a write buffer for storing write data.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoto Sugai, Atsushi Settsu, Saburo Kobayashi
  • Patent number: 6374353
    Abstract: A method of booting up an information processing apparatus is provided. An operating system is divided into a mini operating system (OS) module having a function of bootstrap and an OS main body module having functions other than the function of bootstrap. The mini OS module can be located in a boot block of a boot device, whereas the OS main body module can be located in a file system of the boot device. A firmware or F/W code module stored in a ROM loads the mini OS module into memory when booting up the information processing apparatus. The mini OS module then loads the OS main body module into memory and then initializes the OS main body module.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Atsushi Settsu, Noriyuki Baba, Naoto Sugai