Patents by Inventor Naoto Takebe

Naoto Takebe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093134
    Abstract: Provided is a culture chamber capable of preparing spheroids with a uniform size with high efficiency and having a micro-space structure which is designed to facilitate replacement of a medium and harvesting of cells. The culture chamber includes a plurality of recesses (10) each formed of a bottom portion (11) and an opening portion (12). The bottom portion (11) has one of a hemispherical shape and a truncated cone shape and the opening portion (12) is defined by a wall that surrounds an area from a boundary between the opening portion (12) and the bottom portion (11) to an end of each of the recesses (10), the wall having a taper angle in a range from 1 degree to 20 degrees. An equivalent diameter of the boundary is in a range from 50 ?m to 2 mm and a depth from a bottom of the bottom portion (11) to the end of each of the recesses is in a range from 0.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Yoko Ejiri, Satoru Ayano, Naoto Fukuhara, Hideki Taniguchi, Takanori Takebe
  • Publication number: 20130062758
    Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.
    Type: Application
    Filed: March 16, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
  • Publication number: 20120286411
    Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.
    Type: Application
    Filed: March 16, 2012
    Publication date: November 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato
  • Patent number: 8237295
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Sano, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
  • Publication number: 20110309502
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.
    Type: Application
    Filed: March 21, 2011
    Publication date: December 22, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi SANO, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
  • Publication number: 20050110151
    Abstract: A semiconductor device uses a low-dielectric-constant film whose dielectric constant k is 3.0 or lower for an interlayer film. The semiconductor device includes a suppression mechanism unit that suppresses peeling of the interlayer film.
    Type: Application
    Filed: December 29, 2004
    Publication date: May 26, 2005
    Inventors: Itaru Tamura, Katsuya Murakami, Naoto Takebe
  • Patent number: 6258632
    Abstract: One end of bonding wires made of aluminium, gold, etc., is connected to a plurality of electrode pads formed on the main surface of a semiconductor chip. The other end of these bonding wires is exposed on the surface of the molded resin unit. Connecting electrodes made of aluminium are formed on top of the exposed parts of these bonding wires. The semiconductor chip and external circuitry are connected electrically by means of these connecting electrodes.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoto Takebe
  • Patent number: 5869905
    Abstract: One end of bonding wires made of aluminium, gold, etc., is connected to a plurality of electrode pads formed on the main surface of a semiconductor chip. The other end of these bonding wires is exposed on the surface of the molded resin unit. Connecting electrodes made of aluminium are formed on top of the exposed parts of these bonding wires. The semiconductor chip and external circuitry are connected electrically by means of these connecting electrodes.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: February 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoto Takebe