Patents by Inventor Naoto Tate

Naoto Tate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7288418
    Abstract: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical polishing on the free surface of the working layer.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: October 30, 2007
    Assignee: S.O.O.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate
  • Publication number: 20060189102
    Abstract: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical polishing on the free surface of the working layer.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 24, 2006
    Inventors: Thierry Barge, Andre Auberton-Herve, Hiroji Aga, Naoto Tate
  • Patent number: 7029993
    Abstract: The invention relates to a method for treating substrates (50) for microelectronics or optoelectronics, whereby said substrates comprise a useful layer (52) on at least one of the surfaces thereof. The inventive method includes a mechanical/chemical polishing step occurring on a bare surface (54) of the useful layer and is characterized in that it also comprises a post-curing step in a reductive atmosphere (100) before said polishing step occurs.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: April 18, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate
  • Patent number: 6897124
    Abstract: A bonded wafer 27 and a residual wafer 28 are placed in a state of being superimposed on each other on a susceptor 20 disposed in a heat treatment 10. A Bernoulli chuck 1 is moved to a wafer holding position 60 on a susceptor 20 by driving an arm 56, sucks the bonded wafer 27 positioned on the upper side and then moves to a bonded wafer recovery table 50? to recover the bonded wafer there. Then, similarly, the Bernoulli chuck 1 suction holds the residual wafer 28 at the wafer holding position 60 and then moves to a residual wafer recovery table 50? to recover the residual wafer there. With such a construction adopted, in a method for manufacturing a bonded wafer according to a so-called smart-cut method, not only is the separated bonded wafer recovered suppressing occurrence of a defect, deficiency and contamination, but there is also provided a method for manufacturing a bonded wafer capable of automation suitable for mass production.
    Type: Grant
    Filed: May 27, 2002
    Date of Patent: May 24, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Naoto Tate, Hiroji Aga
  • Patent number: 6846718
    Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: January 25, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Naoto Tate, Susumu Kuwabara, Kiyoshi Mitani
  • Publication number: 20040152283
    Abstract: A bonded wafer 27 and a residual wafer 28 are placed in a state of being superimposed on each other on a susceptor 20 disposed in a heat treatment 10. A Bernoulli chuck 1 is moved to a wafer holding position 60 on a susceptor 20 by driving an arm 56, sucks the bonded wafer 27 positioned on the upper side and then moves to a bonded wafer recovery table 50′ to recover the bonded wafer there. Then, similarly, the Bernoulli chuck 1 suction holds the residual wafer 28 at the wafer holding position 60 and then moves to a residual wafer recovery table 50″ to recover the residual wafer there. With such a construction adopted, in a method for manufacturing a bonded wafer according to a so-called smart-cut method, not only is the separated bonded wafer recovered suppressing occurrence of a defect, deficiency and contamination, but there is also provided a method for manufacturing a bonded wafer capable of automation suitable for mass production.
    Type: Application
    Filed: November 24, 2003
    Publication date: August 5, 2004
    Inventors: Naoto Tate, Hiroji Aga
  • Patent number: 6720640
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: April 13, 2004
    Assignees: Shin-Etsu Handotai Co., Ltd., S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Publication number: 20040063298
    Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 1, 2004
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Naoto Tate, Susumu Kawabara, Kiyoshi Mitani
  • Publication number: 20030219957
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Application
    Filed: May 29, 2003
    Publication date: November 27, 2003
    Applicants: Shin-Etsu Handotai Co., Ltd., S. O. I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Patent number: 6596610
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: July 22, 2003
    Assignees: Shin-Etsu Handotai Co. Ltd., S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Patent number: 6569749
    Abstract: A novel method of generating intrinsic gettering sites in epitaxial wafers employs co-implanting silicon and oxygen into a substrate of the wafer, annealing the substrate at a low temperature, and then depositing the epitaxial layer on a surface of the substrate. The epitaxial deposition acts as an in-situ anneal to form dislocation loops that act as gettering sites. Oxygen precipitate clusters form during the method, which clusters act to anchor the dislocation loops and prevent them from gliding to the wafer surface over time.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: May 27, 2003
    Assignee: SEH America, Inc.
    Inventors: Witawat Wijaranakula, Jallepally Ravi, Naoto Tate
  • Patent number: 6372609
    Abstract: There is provided a method of fabricating an SOI wafer having high quality by hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination and surface roughness are removed maintaining thickness uniformity of the SOI layer. According to the present invention, there are provided a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after bonding heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after delaminating heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; and an SOI wafer fabricated by the methods.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: April 16, 2002
    Assignees: Shin-Etsu Handotai Co., Ltd., Soitec S.A.
    Inventors: Hiroji Aga, Naoto Tate, Kiyoshi Mitani
  • Publication number: 20010046746
    Abstract: There is disclosed a method of fabricating an SOI wafer wherein an oxide film is formed on at least one of two single crystal silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form an ion implanted layer; the ion-implanted surface is brought into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to separate a thin film from the silicon wafer with using the ion implanted layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and then an epitaxial layer is grown on the SOI layer to form a thick SOI layer. There is provided an SOI wafer which has a thick SOI layer with good thickness uniformity and good crystallinity and which is useful for a bipolar device or a power device.
    Type: Application
    Filed: July 16, 2001
    Publication date: November 29, 2001
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Naoto Tate, Kiyoshi Mitani
  • Patent number: 6284629
    Abstract: There is disclosed a method of fabricating an SOI wafer wherein an oxide film is formed on at least one of two single crystal silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form an ion implanted layer; the ion-implanted surface is brought into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to separate a thin film from the silicon wafer with using the ion implanted layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and then an epitaxial layer is grown on the SOI layer to form a thick SOI layer. There is provided an SOI wafer which has a thick SOI layer with good thickness uniformity and good crystallinity and which is useful for a bipolar device or a power device.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: September 4, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Naoto Tate, Kiyoshi Mitani
  • Patent number: 6254933
    Abstract: A method of performing chemical vapor deposition which produces semiconductor crystalline thin films having small transition widths. The method involves the use of a cold-wall type reaction chamber that is equipped with a gas inlet at one end and a gas outlet at the other end and a semiconductor substrate support which supports a semiconductor substrate so that a main surface thereof is horizontal. A reactant gas is caused to flow horizontally through the reaction chamber to effect the growing of a crystalline thin film on the main surface of the semiconductor substrate. The semiconductor substrate is arranged within the reactor chamber within a distance W which is measured from a leading edge of the semiconductor substrate at a most upstream position along a direction toward the gas outlet where W indicates an internal width of the reaction chamber.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: July 3, 2001
    Assignee: Shin-Etsu Handotai, Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 6072164
    Abstract: There is provided a heat-treating method and a radiant heating device by which an object to be heat-treated can be heat-treated at an actually desired temperature regardless of the dopant concentration or resistivity of the object at the time of heat-treating the object with a radiant heating device using a radiation thermometer as a temperature detector. In the method, the object is heat-treated at an actually desired temperature by correcting the temperature of the object in accordance with the dopant concentration or resistivity of the object. In the apparatus, the dopant concentration or resistivity of the object is inputted in advance to a temperature controller and the controller calculates an actual temperature of the object by correcting and computing the temperature of the object detected with the radiation thermometer in accordance with the dopant concentration or resistivity of the object and controls the temperature of the object based on the calculated temperature value.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: June 6, 2000
    Assignee: Shin-Estu Handotai Co., Ltd.
    Inventors: Naoto Tate, Tomoyuki Sakai, Naohisa Toda, Hitoshi Habuka
  • Patent number: 6048793
    Abstract: In a method and an appratus for a thin film growth on a semiconductor crystal substrate, impurities and contaminants absorbed on the inside wall of the reaction vessel are very harmful because these impurities and contaminants will deteriorate the quality of the thin film. A method and an apparatus by which the quantity of these impurities and contaminants absorbed on the inside wall of the reaction vessel can be restrained and removed easily are disclosed in this invention, wherein a semiconductor crystal substrate is mounted in the reaction vessel, and the wall of the reation vessel is cooled forcibly by a coolant while the substrate is under heating procedure to grow a thin film on the substrate by supplying the raw material gas into the reaction vessel. And the temperature of the wall of the reaction vessel during the procedure except the thin film growth is kept higher temperature than the temprature of the wall of the reaction vessel during the thin film growth procedure.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: April 11, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 6022793
    Abstract: A novel method of generating intrinsic gettering sites in epitaxial wafers employs co-implanting silicon and oxygen into a substrate of the wafer, annealing the substrate at a low temperature, and then depositing the epitaxial layer on a surface of the substrate. The epitaxial deposition acts as an in-situ anneal to form dislocation loops that act as gettering sites. Oxygen precipitate clusters form during the method, which clusters act to anchor the dislocation loops and prevent them from gliding to the wafer surface over time.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: February 8, 2000
    Assignee: SEH America, Inc.
    Inventors: Witawat Wijaranakula, Jallepally Ravi, Naoto Tate
  • Patent number: 5938840
    Abstract: In the formation of a thin film on the surface of a semiconductor crystal substrate by using a horizontal type vapor phase growth apparatus, the distribution of the thickness and resistivity of the thin film can be properly obtained by adjusting the concentration distribution of the raw material gas in the mixture gas in the width direction of the reaction vessel over the substrate surface. And in the reaction vessel, carrier gas is supplied from the position close to the transfer port of the substrate, and raw material gas is supplied from the position located in the downstream side of a vortex generation region caused by the flow of the carrier gas.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: August 17, 1999
    Assignee: Shin-Etsu Handotai, Co., Ltd
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 5764353
    Abstract: A method of measuring and monitoring the back side and interior defect density of a wafer from its back side by substantially increasing the back side reflectivity through lapping, etching and controlled back side damage, then measuring defect density with an optical scanner.
    Type: Grant
    Filed: November 29, 1996
    Date of Patent: June 9, 1998
    Assignee: SEH America, Inc.
    Inventors: Naoto Tate, Eva Brown, Michito Sato