Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

Abstract: Disclosed are resist compositions and semiconductor device fabrication methods using the same. The resist composition comprises a hypervalent iodine compound of Chemical Formula 1 below. Wherein R1 to R7 are as defined herein.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.

Abstract: A transparent electric conductor includes titanium oxide doped with aluminum and at least one other dopant: either in the form Ti1-a-bAlaXbOy, where X is a dopant or a mixture of dopants selected from the group consisting of Nb, Ta, W, Mo, V, Cr, Fe, Zr, Co, Sn, Mn, Er, Ni, Cu, Zn and Sc, a is in the range 0.01 to 0.50, and b is in the range 0.01 to 0.15; or in the form Ti1-aAlaFcOy-c, where a is in the range 0.01 to 0.50, and c is in the range 0.01 to 0.10. With the above composition, the electrical conductivity and the light transmittance are suitable for use of the transparent electric conductor in various applications, in particular as a transparent electrode of an electronic device.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.