Abstract: In a semiconductor electrically erasable and writable non-volatile memory device, a memory cell array 14 includes a test memory region 142 for a writing test, and there are provided a writing test circuit for generating a writing test signal WTEST, a write voltage-detecting circuit 18 for generating a voltage-detecting signal WREN when a writing voltage supplied to the region 142 is less than a reference value at the time of writing test, and an output buffer circuit 15 which switches it to a test output mode in response to the supply of the writing test signal WTEST and outputs a write inhibit information in response to the supply of voltage-detecting signal WREN.

Abstract: A comparator circuit of the present invention comprises first and second bipolar type transistors for amplification of the input and reference voltages and first to fourth MOS type transistors for comparison and latching of the amplified input and reference voltages according to the first driving signal and fifth and sixth MOS type transistors provided between the first/second bipolar transistors and the first to fourth MOS type transistors for turning on and off according to the second driving signal, all on a single stage.