Patents by Inventor Naoya FUKUCHI

Naoya FUKUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system and method of controlling cache memory
    Patent number: 10540278
    Abstract: According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: January 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Fukuchi
  • Memory system and method for controlling nonvolatile memory
    Patent number: 10310810
    Abstract: A memory system including a nonvolatile memory and a controller configured to control the nonvolatile memory, and a method executed by the memory system, wherein the controller fetches a first command in a submission queue on a memory of a host to a first queue in the memory system and executes the first command, checks contents of a subsequent command in the submission queue or another submission queue while leaving the subsequent command in the submission queue or the other submission queue, fetches the subsequent command to a second queue in the memory system, and executes the subsequent command and the first command in parallel, when the subsequent command is a command executable during the execution of the first command.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Naoya Fukuchi
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20180285073
    Abstract: According to one embodiment, a memory system fetches a first command in a submission queue on a memory of a host to a first queue in the memory system and executes the first command. The memory system checks contents of a subsequent command in the submission queue or another submission queue while leaving the subsequent command in the submission queue or the other submission queue. The memory system fetches the subsequent command to a second queue in the memory system and executes the subsequent command and the first command in parallel, when the subsequent command is a command executable during the execution of the first command.
    Type: Application
    Filed: September 13, 2017
    Publication date: October 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Naoya FUKUCHI
  • MEMORY SYSTEM AND METHOD OF CONTROLLING CACHE MEMORY
    Publication number: 20180210831
    Abstract: According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya FUKUCHI
  • Memory system and method of controlling cache memory
    Patent number: 9959206
    Abstract: According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Fukuchi
  • MEMORY SYSTEM AND METHOD OF CONTROLLING CACHE MEMORY
    Publication number: 20160342511
    Abstract: According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
    Type: Application
    Filed: August 31, 2015
    Publication date: November 24, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Naoya FUKUCHI