Abstract: An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.

Abstract: An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.

Abstract: A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying.

Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: An information processing apparatus including a plurality of mutually connected system boards, wherein each of the system boards includes: a plurality of processors; and a plurality of memories each of which stores data and directory information corresponding to the data, and corresponds to any one of the processors, and wherein each of the plurality of processors, upon receiving a read request for data stored in a memory corresponding to the own processor from another processor, performs an exclusive logical sum operation on identification information included in the read request and identifying the another processor and a check bit included in the directory information and identifying a processor which holds target data of the read request, increments a count value included in the directory information and indicating the number of processors which hold the target data, and sets presence information included in the directory information and indicating a system board which includes the another processor.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: A cache memory control device includes cache memories shared by arithmetic processing units, buses shared by the arithmetic processing units to transfer data, an instruction execution unit that accesses the cache memories to execute an access instruction from the arithmetic processing unit, and transfers data from the cache memory to the bus, an instruction feeding unit that feeds the access instruction to the instruction execution unit while inhibiting feeding of a subsequent access instruction for the cache memory accessed in the preceding access instruction in an execution period of the preceding access instruction and inhibiting feeding of a subsequent access instruction using the same bus as the preceding access instruction in a predetermined period, and a timing control unit that, depending on the type of the subsequent access instruction, controls the instruction executing unit to delay the transfer of the data from the cache memory to the bus.

Abstract: A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a CPU node without being intervened by the memory management part.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: A device includes: a request-storage unit including entries configured to store requests and stopping issuance of a stored request when a flag is set based on an input configuration notification, in which the request-storage unit outputs a warning notification when the request stored in any of the entries has not been processed for more than a predetermined amount of time; a derived request-storage unit including derived entries configured to store derived requests derived from processing of requests stored in the request-storage unit; an arbitrating unit configured to arbitrate requests stored in the request-storage unit and derived requests stored in the derived request-storage unit, and to output the configuration notification based on the warning notification output from the request-storage unit; and a request-processing unit configured to process requests or derived requests arbitrated by the arbitrating unit, and to request-storage of derived requests derived by processing requests into the derived-stor

Abstract: A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.

Abstract: A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying.

Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.

Abstract: A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Abstract: A processor includes: a first storage that stores data stored in a main storage; a processor that outputs an instruction for loading data from the main storage into the first storage; a second storage that holds a instruction until the first storage receives the data requested by the instruction; a first controller that reads the data requested by an instruction from the first storage and transfers the requested data to the processor, when the requested data is in the first storage, or but, transfers the received instruction to the main storage, when the requested data is not in the first storage and an instruction requesting the same data as the requested data is not in the second storage; and a second controller that completes reading the data requested by an instruction, when an instruction requesting the same data as the requested data is in the second storage.

Abstract: An apparatus for controlling a cache memory that stores therein data transferred from a main storing unit includes a computing processing unit that executes a computing process using data, a connecting unit that connects an input portion and an output portion of the cache memory, a control unit that causes data in the main storing unit to be transferred to the output portion of the cache memory through the connecting unit when the data in the main storing unit is input from the input portion of the cache memory into the cache memory, and a transferring unit that transfers data transferred by the control unit to the output portion of the cache memory, to the computing processing unit.

Abstract: When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.

Abstract: A cache memory control device includes cache memories shared by arithmetic processing units, buses shared by the arithmetic processing units to transfer data, an instruction execution unit that accesses the cache memories to execute an access instruction from the arithmetic processing unit, and transfers data from the cache memory to the bus, an instruction feeding unit that feeds the access instruction to the instruction execution unit while inhibiting feeding of a subsequent access instruction for the cache memory accessed in the preceding access instruction in an execution period of the preceding access instruction and inhibiting feeding of a subsequent access instruction using the same bus as the preceding access instruction in a predetermined period, and a timing control unit that, depending on the type of the subsequent access instruction, controls the instruction executing unit to delay the transfer of the data from the cache memory to the bus.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.