Patents by Inventor Naoya Kimura

Naoya Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070091708
    Abstract: A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predetermined time from the reference timing until a second predetermined time has elapsed and selects a port B during other periods. The control circuit generates a port-A delayed clock signal in the period in which the port A is selected. The control circuit generates a port-B delayed clock signal during the period from elapse of the second predetermined time until a third predetermined time has elapsed. The control circuit generates a conflict monitoring signal during the period from the reference timing until the second predetermined time has elapsed. When a clock signal is supplied from the port B while the conflict monitoring signal is being generated, the port-B delayed clock signal is masked while the conflict monitoring signal is being generated.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 26, 2007
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Seiichirou Ishimoto, Kunio Takamatsu, Naoya Kimura
  • Publication number: 20070013623
    Abstract: A display includes capacitive display elements, output drivers, scan switches, precharge switches, and a precharge stopper. The drivers provide drive currents or voltages corresponding to display data, thereby driving the display elements correspondingly to the data. The precharge stopper determines whether display data corresponds to a specific state and prevents the display element from being precharged when the display data corresponds to the specific state.
    Type: Application
    Filed: June 7, 2006
    Publication date: January 18, 2007
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Naoya Kimura, Hiroyoshi Ichikura
  • Publication number: 20060023002
    Abstract: A color balancing circuit for a flat panel display such as an electroluminescent display generates a primary current that can be varied to adjust the overall brightness of the display. Three currents related to the primary current by selectable ratios are generated, by current mirror circuits, for example; the ratios can be individually varied to adjust the color balance. Driving currents are generated from the three adjusted currents, by mirroring the adjusted currents, for example, and are used to drive display elements that emit light in the three primary colors. Image brightness and color balance can accordingly be adjusted separately, even though both are adjusted by adjusting the driving current. Circuit size is reduced in that the same primary current is used for all three primary colors.
    Type: Application
    Filed: May 12, 2005
    Publication date: February 2, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Tetsuro Hara, Naoya Kimura, Takayuki Shimizu, Akira Kondo, Haruyo Takayanagi, Shinichi Satoh
  • Publication number: 20060022968
    Abstract: A display panel driver has two driver circuits that drive separate halves of a display panel. Each driver circuit occupies a separate integrated circuit chip. The driver has a screen saving mode in which each driver circuit displays an independent screen saving image that moves in synchronization with a timing signal. The timing signal is generated in one driver circuit and transmitted by a chip-to-chip interface to the other driver circuit. The two screen saving images are thereby coordinated to create what appears to be a single screen saving display.
    Type: Application
    Filed: July 14, 2005
    Publication date: February 2, 2006
    Inventors: Akira Kondo, Naoya Kimura, Haruyo Takayanagi, Tetsuro Hara, Takayuki Shimizu, Hiroyoshi Ichkura
  • Publication number: 20060022914
    Abstract: A driving circuit drives a display panel having a matrix of picture elements and electrodes. The driving circuit includes a memory storing compensation data for compensating for position-dependent brightness differences between the picture elements. The brightness differences are due to the stray resistance and capacitance of the picture elements and electrodes. A correction circuit modifies image data according to the compensation data to generate control signals, which are used to control drivers that drive the picture elements via the electrodes. The modified image data produce a display with an even average brightness over the entire display panel.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 2, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Naoya Kimura, Tetsuro Hara, Akira Kondo, Takayuki Shimizu, Haruyo Takayanagi, Shinichi Fukuzako, Ichirou Takayama
  • Publication number: 20060022911
    Abstract: Disclosed is a drive circuit for a panel display device for driving light-emitting devices arranged at respective intersections between a plurality of data lines and a plurality of scan lines. This drive circuit includes a voltage control circuit for charging the light-emitting devices to a voltage necessary for light emission by connecting the data lines to a predetermined power supply potential in a rising period prior to a period for selectively causing the light-emitting devices to emit light; and a drive control circuit for selectively connecting the data lines to a constant current source after the rising period.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Shinichi Satoh, Naoya Kimura, Tetsuro Hara
  • Publication number: 20060022913
    Abstract: The object of the invention is elimination of an occurrence of instantaneous light in the center part of a display, a border between the upper half and the lower half of the display. An scanning method of the display, dividing the display panel to a first filed and a second filed, starts a counter therein, synchronized with the timing of driving a first row electrode of the first filed thereof, and drives a first row electrode of the second filed thereof, every time the counter value changes.
    Type: Application
    Filed: August 1, 2005
    Publication date: February 2, 2006
    Applicant: Oki Electric Industry Corporation
    Inventors: Haruyo Takayanagi, Akira Kondo, Tetsuro Hara, Naoya Kimura, Takayuki Shimizu, Shuji Furuichi
  • Publication number: 20050069025
    Abstract: A receiver includes a channel-matched-filter for outputting a Rake-combining result from a digital spread spectrum signal; a carrier recovery circuit which removes an offset of a carrier wave from the combining result; a correlation circuit which detects correlation; a symbol timing detection circuit which extracts a symbol from the correlation; a symbol determination circuit which regenerates data from the symbol; a framer circuit which discriminates a frame configuration; and a symbol timing recovery circuit which generates a timing phase for each of symbol timings. The channel-matched-filter performs multi-phasing compensation and, in accordance with a timing phase from the symbol timing recovery circuit, performs synchronization tracking.
    Type: Application
    Filed: May 6, 2004
    Publication date: March 31, 2005
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Naoya Kimura
  • Patent number: 6597627
    Abstract: Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: July 22, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuichi Arata, Naoya Kimura, Hideaki Odagiri
  • Publication number: 20030031080
    Abstract: Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.
    Type: Application
    Filed: March 25, 2002
    Publication date: February 13, 2003
    Inventors: Yuichi Arata, Naoya Kimura, Hideaki Odagiri
  • Patent number: 6469544
    Abstract: A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: October 22, 2002
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Naoya Kimura
  • Publication number: 20020008548
    Abstract: A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.
    Type: Application
    Filed: May 16, 2001
    Publication date: January 24, 2002
    Inventor: Naoya Kimura
  • Patent number: 4865954
    Abstract: The present invention provides a method for forming a metal image in which a resist film is provided at an image portion and then etching processing is performed to thereby form the metal image comprising the steps of: (1) forming an image comprised of concave surface portions on a metal surface; (2) forming a resist film on the metal surface; and (3) exposing the resist film to such an extent that at the concave portions of the resist film is not made wholly soluble.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: September 12, 1989
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: Yoshichi Hagiwara, Naoya Kimura, Kenji Emori