Patents by Inventor NAOYA KIYAMA

NAOYA KIYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162092
    Abstract: A manufacturing method of a semiconductor device includes: forming a plurality of element structures in a form of matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between the element structures adjacent to each other by pressing a pressing member against a second surface of the semiconductor wafer opposite to the first surface along the boundary; and dividing the semiconductor wafer along the boundary by pressing a dividing member against the semiconductor wafer on a first surface side along the boundary.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 16, 2024
    Inventors: Yuji NAGUMO, Masashi UECHA, Masaru OKUDA, Masatake NAGAYA, Mitsuru KITAICHI, Akira MORI, Naoya KIYAMA, Masakazu TAKEDA
  • Publication number: 20240038711
    Abstract: A semiconductor device includes a semiconductor substrate and a metal layer disposed on a surface of the semiconductor substrate. The metal layer includes a first metal layer and a second metal layer. The second metal layer covers a surface of the first metal layer and has a higher solder wettability than the first metal layer. The second metal layer is exposed on a main surface of the metal layer. The first metal layer is exposed on a side surface of the metal layer. The metal layer has a protruding portion on the main surface. The protruding portion extends to make one round along an outer peripheral edge of the main surface.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: TERUAKI KUMAZAWA, MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20240038590
    Abstract: A semiconductor device includes a semiconductor substrate having a quadrangular shape when viewed from above and having a front surface, a rear surface opposite to the front surface, and four side surfaces connecting the front surface and the rear surface. Each of the side surfaces has a step section in which a plurality of protruding portions and a plurality of recessed portions alternately and repeatedly appear along a direction in which a peripheral edge of the front surface of the semiconductor substrate extends.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20240030056
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate having a plurality of element regions and having a first surface and a second surface opposite to each other, forming a crack extending in a thickness direction of the semiconductor substrate along a boundary between the plurality of element regions by pressing a pressing member against the first surface of the semiconductor substrate along the boundary, forming a metal film over the plurality of element regions on the first surface of the semiconductor substrate after the forming of the crack, and dividing the semiconductor substrate and the metal film along the boundary by pressing a dividing member against the semiconductor substrate along the boundary from a direction facing the second surface of the semiconductor substrate after the forming of the metal film.
    Type: Application
    Filed: May 26, 2023
    Publication date: January 25, 2024
    Inventors: MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA