Abstract: A producing method of a handle wafer for a bonded wafer produced by bonding an active wafer and the handle wafer through an insulation film includes: preparing a handle wafer body made from a monocrystalline silicon wafer; forming an oxide film on the handle wafer body; depositing a polycrystalline silicon layer on the oxide film; forming a protective oxide film on a surface of the polycrystalline silicon layer; and polishing to remove the protective oxide film and polishing the polycrystalline silicon layer.

Abstract: A silicon wafer is provided in which a dopant is phosphorus, resistivity is 1.2 m?·cm or less, and carbon concentration is 3.5×1015 atoms/cm3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

Abstract: A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 m?·cm to 1.2 m?·cm, and carbon concentration is 3.0×1016 atoms/cm3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

Abstract: An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m ?·cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30? to 0°55? in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cm2 of a density of a hillock defect generated thereon.

Abstract: A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 m?·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5? to 0°25? with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).

Abstract: A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 m?·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5? to 0°25? with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).

Abstract: An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m ?·cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30? to 0°55? in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cm2 of a density of a hillock defect generated thereon.

Abstract: A method includes: a step of forming an oxide film on a backside of a silicon wafer; a step of removing the oxide film present at an outer periphery of the silicon wafer; a step of argon annealing in which a heat treatment is performed in an argon gas atmosphere; and a step of forming an epitaxial film on a surface of the silicon wafer, the step of forming the epitaxial film including: a step of pre-baking in which the silicon wafer is subjected to a heat treatment in an gas atmosphere containing hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and a step of growing the epitaxial film on the surface of the silicon wafer.

Abstract: A method includes: a step of forming an oxide film on a backside of a silicon wafer; a step of removing the oxide film present at an outer periphery of the silicon wafer; a step of argon annealing in which a heat treatment is performed in an argon gas atmosphere; and a step of forming an epitaxial film on a surface of the silicon wafer, the step of forming the epitaxial film including: a step of pre-baking in which the silicon wafer is subjected to a heat treatment in an gas atmosphere containing hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and a step of growing the epitaxial film on the surface of the silicon wafer.

Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.

Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.

Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.

Abstract: A method of manufacturing an epitaxial silicon wafer including a silicon wafer having a surface added with phosphorus and an epitaxial film provided on the surface includes adjusting an in-plane thickness distribution of the epitaxial film formed on the surface of the silicon wafer based on an in-plane resistivity distribution of the silicon wafer before an epitaxial growth treatment.

Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.

Abstract: A method of manufacturing an epitaxial silicon wafer including a silicon wafer having a surface added with phosphorus and an epitaxial film provided on the surface includes adjusting an in-plane thickness distribution of the epitaxial film formed on the surface of the silicon wafer based on an in-plane resistivity distribution of the silicon wafer before an epitaxial growth treatment.