Abstract: An attention calling device includes a memory and a hardware processor coupled to the memory. The hardware processor is configured to: acquire information regarding obstacles around a moving object detected by a sensor included in the moving object; calculate a potential risk that is a degree to which attention needs to be paid for each of the obstacles around the moving object, based on the acquired information regarding the obstacles and a moving state of the moving object; and present, to an occupant of the moving object, information for calling attention to an obstacle having a potential risk exceeding a predetermined value, based on a calculated potential risk of each of the obstacles.

Abstract: An attention calling device includes a memory and a hardware processor coupled to the memory. The hardware processor is configured to: acquire information regarding obstacles around a moving object detected by a sensor included in the moving object; calculate a potential risk that is a degree to which attention needs to be paid for each of the obstacles around the moving object, based on the acquired information regarding the obstacles and a moving state of the moving object; and present, to an occupant of the moving object, information for calling attention to an obstacle having a potential risk exceeding a predetermined value, based on a calculated potential risk of each of the obstacles.

Abstract: Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.

Abstract: Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.