Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.

Abstract: According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data.

Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.

Abstract: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store.

Abstract: A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: According to one embodiment, a nonvolatile memory device includes a core unit and a peripheral circuit unit. The core unit is configured to be capable of storing data. The peripheral circuit unit is configured to program and read the data to and from the core unit. The peripheral circuit unit is configured to generate an internal clock having a first period. The peripheral circuit unit is configured to change the first period to be a second period after being input a first command and a second command within an interval.

Abstract: A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other.

Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: Provided is a non-volatile semiconductor storage device according to one embodiment including: a memory cell array where memory cells capable of storing data of three or more levels are arrayed; a flag cell which is provided in an access prevention area where external access to the memory cell array is prevented; a flag data generating unit which generates flag data which is to be written in the flag cell based on a written state of the memory cell array; and an access prevention cancelling unit which permits external reading of the flag data based on an externally applied command.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other.

Abstract: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.