Patents by Inventor Naoya Yamakawa

Naoya Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8732443
    Abstract: A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out the program, and a data acquiring circuit connected to an external program processing device, for acquiring the program from the external program processing device to write into the internal memory, wherein the CPU, the internal memory, a debug processing circuit, and the data acquiring circuit are integrally mounted on the same semiconductor substrate.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Naoya Yamakawa, Yasunori Nagata, Tomofumi Watanabe
  • Patent number: 7512057
    Abstract: Disclosed is a laser pulse controlling circuit that, when the laser device is driven with laser pulses having the first and the second illumination levels, causes the first and the second illumination level setting units to set the first and the second illumination levels corresponding to a predetermined ratio of the first illumination level to the second illumination level, wherein the laser pulse controlling circuit, based on regularity that the relation between: a manipulated variable for causing the second illumination level setting unit to execute adjustment of the second illumination level; and the inverse of the ratio, with reference to the first illumination level, is a straight line that necessarily passes one point for a predetermined first illumination level, and that the slope of the straight line is proportional to an arbitrary first illumination level, calculates the manipulated variable that is correlated with the first illumination level corresponding to the optical disk, and with the inverse
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: March 31, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Katsuya Tanoue, Kenichi Ikegami, Naoya Yamakawa
  • Patent number: 7434103
    Abstract: A program processing device that improves efficiency when debugging software. The processing device includes a CPU core and a monitor circuit, which is connected to an internal bus that is used by the CPU core to access a memory area. The monitor circuit monitors the internal bus and checks whether a designated variable in the program has been rewritten. When the designated variable has been rewritten, the monitor circuit stores the updated data and transmits variable information stored in an internal register to a debugging tool in a predetermined transmission cycle.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 7, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Suzuki, Naoya Yamakawa
  • Publication number: 20080109633
    Abstract: A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out the program, and a data acquiring circuit connected to an external program processing device, for acquiring the program from the external program processing device to write into the internal memory, wherein the CPU, the internal memory, a debug processing circuit, and the data acquiring circuit are integrally mounted on the same semiconductor substrate.
    Type: Application
    Filed: November 6, 2007
    Publication date: May 8, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Naoya Yamakawa, Yasunori Nagata, Tomofumi Watanabe
  • Publication number: 20070274191
    Abstract: Disclosed is a laser pulse controlling circuit that, when the laser device is driven with laser pulses having the first and the second illumination levels, causes the first and the second illumination level setting units to set the first and the second illumination levels corresponding to a predetermined ratio of the first illumination level to the second illumination level, wherein the laser pulse controlling circuit, based on regularity that the relation between: a manipulated variable for causing the second illumination level setting unit to execute adjustment of the second illumination level; and the inverse of the ratio, with reference to the first illumination level, is a straight line that necessarily passes one point for a predetermined first illumination level, and that the slope of the straight line is proportional to an arbitrary first illumination level, calculates the manipulated variable that is correlated with the first illumination level corresponding to the optical disk, and with the inverse
    Type: Application
    Filed: April 1, 2005
    Publication date: November 29, 2007
    Inventors: Katsuya Tanoue, Kenichi Ikegami, Naoya Yamakawa
  • Patent number: 7203819
    Abstract: A program processing device that improves efficiency when debugging software. The processing device includes a CPU core and a break circuit, which is connected to an internal bus that is used by the CPU core to access a memory area. The break circuit monitors the internal bus and checks whether a designated variable in the program has been rewritten. When the designated variable has been rewritten, the break circuit breaks the operation of the CPU core.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: April 10, 2007
    Assignee: Sony Electric Co., Ltd
    Inventors: Takayuki Suzuki, Naoya Yamakawa
  • Publication number: 20050044345
    Abstract: A program processing device that improves efficiency when debugging software. The processing device includes a CPU core and a break circuit, which is connected to an internal bus that is used by the CPU core to access a memory area. The break circuit monitors the internal bus and checks whether a designated variable in the program has been rewritten. When the designated variable has been rewritten, the break circuit breaks the operation of the CPU core.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 24, 2005
    Inventors: Takayuki Suzuki, Naoya Yamakawa
  • Publication number: 20050044452
    Abstract: A program processing device that improves efficiency when debugging software. The processing device includes a CPU core and a monitor circuit, which is connected to an internal bus that is used by the CPU core to access a memory area. The monitor circuit monitors the internal bus and checks whether a designated variable in the program has been rewritten. When the designated variable has been rewritten, the monitor circuit stores the updated data and transmits variable information stored in an internal register to a debugging tool in a predetermined transmission cycle.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 24, 2005
    Inventors: Takayuki Suzuki, Naoya Yamakawa