Patents by Inventor Naoya Yasuda

Naoya Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11381086
    Abstract: A power management system, which has a holding function capable of holding power in the form of storable energy, and a supply function for supplying power procured from a contractor to the holding function, sets a utilizable range of storable energy held by the holding function. In the setting, if an amount of storable energy held by the holding function exceeds a predetermined amount, an excess of the storable energy exceeding the predetermined amount is set as utilizable storable energy.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Naoya Yasuda, Shinichi Yokoyama, Tomohide Haraguchi, Takashi Sone
  • Publication number: 20200403419
    Abstract: The present invention provides a power management system for managing a power unit, the power management system comprising: an obtaining unit configured to obtain utilization plan information of the power unit pre-registered by a user of the power unit; a creation unit configured to create an operation plan of the power unit based on the utilization plan information obtained by the obtaining unit; and a setting unit configured to set an incentive to the user according to the utilization plan information obtained by the obtaining unit.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Shinichi Yokoyama, Tomohide Haraguchi, Naoya Yasuda
  • Publication number: 20200361336
    Abstract: A management apparatus that manages an electric power device of an electric power consumer, comprises: an obtaining unit configured to obtain characteristic information of the electric power device as information related to an environmental load; and a planning unit configured to plan a priority rank of an operation of the electric power device in utilization of electric power of the electric power device based on the characteristic information obtained by the obtaining unit.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi YOKOYAMA, Tomohide HARAGUCHI, Naoya YASUDA, Hiromasa SHIGETA, Keiichi IGUCHI
  • Publication number: 20200328595
    Abstract: A power management system, which has a holding function capable of holding power in the form of storable energy, and a supply function for supplying power procured from a contractor to the holding function, sets a utilizable range of storable energy held by the holding function. In the setting, if an amount of storable energy held by the holding function exceeds a predetermined amount, an excess of the storable energy exceeding the predetermined amount is set as utilizable storable energy.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 15, 2020
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Naoya Yasuda, Shinichi Yokoyama, Tomohide Haraguchi, Takashi Sone
  • Patent number: 7763966
    Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
  • Patent number: 7622799
    Abstract: A semiconductor device in which memory chips are stacked on the surface of a wiring substrate has a microcomputer chip and an interposer chip arranged on the surface of the memory chip. The pads of the microcomputer chip and the pads of the interposer chip are arranged almost circularly and are connected by bonding wires.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Soshi Kuroda, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando
  • Publication number: 20080217750
    Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
  • Publication number: 20070170573
    Abstract: The semiconductor device with which bonding wires cannot contact easily is offered. In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 26, 2007
    Inventors: Soshi KURODA, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando
  • Patent number: 6713882
    Abstract: The resin sealing apparatus includes a mold that has a main cavity into which a portion of a semiconductor device to be sealed with a resin is disposed. Furthermore, an external-shape regulating member is detachably accommodated in the main cavity of the mold to form a new cavity inside the main cavity.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: March 30, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Naoya Yasuda
  • Publication number: 20030052418
    Abstract: The resin sealing apparatus includes a mold that has a main cavity into which a portion of a semiconductor device to be sealed with a resin is disposed. Furthermore, an external-shape regulating member is detachably accommodated in the main cavity of the mold to form a new cavity inside the main cavity.
    Type: Application
    Filed: March 6, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoya Yasuda