Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Abstract: An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

Abstract: An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.

Abstract: A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.