Abstract: A semiconductor device includes a receiving terminal for receiving a signal transmitted through a signal transmission line, a reference plane voltage terminal connected to a refence plane as a refence for the signal on the signal transmission line and a voltage generating circuit configured to generate a refence plane voltage to be supplied to the reference plane voltage terminal based on the signal received by the receiving terminal.

Abstract: In an operational amplifier constituted by a differential stage which receives two input signals IN- and IN+ and outputs a signal NGP corresponding to the potential difference, a level shift stage which receives the signal NGP and outputs a level-shifted signal NGN, and an output stage which receives the signals NGP and NGN and outputs a signal OUT obtained by amplifying the potential difference between the two input signals, the level shift stage is formed from a DDA. Letting A1, A2, and A3 be the gains of the DDA, the input signal NGP, output signal NGN, and bias voltages VBP and VBN have a linear relation given by A3{A1(VBN-NGN)-A2(VBP-NGP)}=NGN. This maximizes the current drivability of a transistor TN1 on the output stage and controls the punch-through current flowing between transistors TP1 and TN1.

Abstract: In a comparator circuit comprised of a feedback amplifier and a differential amplifier AMP1, the feedback amplifier includes input transistors Tr1 to Tr4. Gates of the transistors Tr1 and Tr2 are respectively inputted with first and second inverted inputs, and gates of the transistors Tr3 and Tr4 are inputted with first and second non-inverted inputs. First ends of current paths of the transistors Tr3 and Tr4 are connected in common, and ends of current paths of transistors Tr1 and Tr2 are connected in common. Second ends of the current paths of the transistors Tr1 to Tr4 are connected in common to a constant current source. The first and second inverted inputs are supplied with a reference voltage, and the first and second non-inverted inputs are respectively supplied with the non-inverted and inverted outputs of the differential amplifier AMP1.

Abstract: The present invention provides a D/A converter which has a small area in the chip, a linear current output and a high-speed operation. Each of resistors R.sub.11 -R.sub.n1 in a resistor train 11a is composed of four MOS transistors which are connected in parallel with each other and each of resistors R.sub.12 -R.sub.n2 in a resistor train 11b is composed of four MOS transistors which are connected in parallel with each other. Between the connecting nodes of the resistor trains 11a, 11b, MOS transistors ST.sub.11, ST.sub.12, ST.sub.13, ST.sub.14 -ST.sub.n1, ST.sub.n2, ST.sub.n3 and ST.sub.n4 which serve as switches and resistors are connected. All the MOS transistors have the same conductive type and size. Gate control signals C.sub.11 -C.sub.n1 ; C.sub.12 -C.sub.n2 turn MOS transistors ON but each of them has a different voltage value. A current difference between the output terminals Za and Zb is converted into a voltage difference by an operational amplifier or the like.