Patents by Inventor Naoyuki Itakura

Naoyuki Itakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080136810
    Abstract: In the present invention, during a 1H period excluding a blanking period (1HB) constituting a line display period, pixel data pulses of RGB (61B to 61R) are successively supplied for each color to corresponding signal lines for color display of one pixel line. A control circuit (40) of select switches connected to the signal lines (6-1 to 6-n) supplies permission pulses (63B to 63R) for supply of data to signal lines when displaying one color among RGB to select switches (TMG), and turns on the select switch (TMG) of the signal line corresponding to another color to be displayed later in the same line display period during the period of this application by a precharge pulse (62G or 62R) having a time duration shorter than the supply time of the pixel data of the other color (T2 or T3) to previously precharge the signal line of the other color to the predetermined potential.
    Type: Application
    Filed: August 20, 2004
    Publication date: June 12, 2008
    Applicant: Sony Corporation
    Inventors: Naoyuki Itakura, Hiroaki Ichikawa, Toshikazu Maekawa
  • Publication number: 20070188431
    Abstract: A display device having a pixel section pixel circuits, scan lines, capacity lines, a drive circuit driving the scan lines and the capacity lines selectively, a generation circuit generating a common voltage signal switching in level at a predetermined cycle, and a correction circuit correcting the signals driving the capacity lines of the drive circuit, wherein each pixel circuit contains a display element and holding capacitor, a first pixel electrode of the display element pixel cell, a first electrode of the holding capacitor, and one terminal of the switching element are connected, a second electrode of the holding capacitor is connected to the capacity lines arrayed in a corresponding row, and the common voltage signal is applied in a second pixel electrode of the display element.
    Type: Application
    Filed: August 3, 2006
    Publication date: August 16, 2007
    Inventors: Tomohiko Sato, Naoyuki Itakura, Takeya Takeuchi, Tomoyuki Fukano
  • Publication number: 20070057887
    Abstract: A display device having a pixel section including a plurality of pixel circuits arrayed in a matrix, a plurality of scan lines, a plurality of capacity lines, a plurality of signal lines, a drive circuit, and a generation circuit generating a small amplitude common voltage signal switching in level at a predetermined cycle, wherein each pixel circuit arranged at the pixel section contains a display element having a first pixel electrode and a second pixel electrode and a storage capacitor having a first electrode and a second electrode, the first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected, the second electrode of the storage capacitor is connected to the capacity lines arrayed in a corresponding row, and the common voltage signal is applied in a second pixel electrode of the display element.
    Type: Application
    Filed: August 16, 2006
    Publication date: March 15, 2007
    Inventors: Naoyuki Itakura, Tomoyuki Fukano, Yoshiharu Nakajima, Tomohiko Sato, Takeya Takeuchi
  • Publication number: 20040189681
    Abstract: A display device able to select a driving capability corresponding to a plurality of resolutions, able to be driven in accordance with the purpose, and able to realize a lower power consumption, and a method of driving the same, providing a vertical drive circuit for processing for successively scanning scan lines in a row direction by scan pulses and successively selecting pixel circuits connected to the scan lines in units of rows in a VGA mode and for processing for successively scanning the scan lines for every adjacent plurality of scan lines in the row direction and successively selecting pixel circuits connected to the plurality of scan lines in units of the plurality of rows in a QVGA mode.
    Type: Application
    Filed: February 10, 2004
    Publication date: September 30, 2004
    Inventors: Naoyuki Itakura, Hiroaki Ichikawa