Patents by Inventor Naoyuki Kanai

Naoyuki Kanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230298977
    Abstract: A conductive member constituting a wiring structure includes a first bonding section bonded to an electronic component, a second bonding section bonded to a connection target for the electronic component, and a raised section that protrudes upward from the first bonding section and is connected to the second bonding section. The conductive member has a wire member passage through which a wire member passes, and which is provided in at least a part of the raised section. The wire member passage enables the wire member to be disposed along the raised section from the first bonding section to the second bonding section such that the wire member intersects a surface of the raised section.
    Type: Application
    Filed: January 30, 2023
    Publication date: September 21, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hitoshi NAKATA, Naoyuki KANAI, Yuichiro HINATA
  • Publication number: 20230260951
    Abstract: A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.
    Type: Application
    Filed: December 28, 2022
    Publication date: August 17, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hitoshi NAKATA, Yuichiro HINATA, Naoyuki KANAI
  • Publication number: 20230187376
    Abstract: A semiconductor module, including: a terminal laminated portion having a first terminal, an insulating member, and a second terminal that are laminated in that order to one another in a laminating direction; and a thermally anisotropic member disposed between the insulating member and the second terminal, the thermally anisotropic member having a thermal conductivity that is higher in a planar direction perpendicular to the laminating direction than in the laminating direction.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 15, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki KANAI, Yuma MURATA
  • Publication number: 20230142695
    Abstract: A semiconductor device includes an insulated circuit board having a conductive pattern layer, a sintered member disposed on the conductive pattern layer, a semiconductor chip placed on the sintered member, and a coating material covering the semiconductor chip. The sintered member has, on a surface thereof opposite to the conductive pattern layer, a frame shaping the outer edge of a recess. The semiconductor chip is mounted in the recess such that its top face is located closer to the conductive pattern layer than a top end of the frame.
    Type: Application
    Filed: September 27, 2022
    Publication date: May 11, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro HINATA, Naoyuki KANAI, Takashi SAITO
  • Patent number: 11610826
    Abstract: A semiconductor module is provided with: a case having a frame that surrounds a substrate and a terminal block formed extending inward from an inner wall surface of the frame; a terminal having one end extending outward from the frame, and another end extending inward from the frame and being secured to a top face of the terminal block; a wiring member that electrically connects the terminal and a semiconductor element on the substrate; and an encapsulating resin that encapsulates the other end of the terminal, the wiring member, and the semiconductor element inside the case. A hole is formed in the top face of the terminal block. The hole is filled with the encapsulating resin, and is positioned closer to the inner wall surface of the frame than a bonding part between the terminal and the wiring member.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 21, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Kanai, Yuichiro Hinata, Yuta Tamai
  • Publication number: 20230069967
    Abstract: A semiconductor apparatus includes a semiconductor element, a control terminal electrically connected to a top electrode of the semiconductor element through a wiring member, and a case member in which at least a portion of the control terminal is embedded and which defines a space for housing the semiconductor element. The control terminal includes a pad to which the wiring member is connected. The case member includes a wiring member positioning part raised on the case member as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad.
    Type: Application
    Filed: July 28, 2022
    Publication date: March 9, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Nobuhiro HIGASHI, Daiki YOSHIDA, Yuma MURATA, Naoyuki KANAI
  • Publication number: 20220415729
    Abstract: There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 29, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yuma MURATA, Naoyuki KANAI
  • Publication number: 20220415749
    Abstract: A semiconductor device includes a baseplate and a case which includes an external wall surrounding an internal space and a dividing wall extending in a first direction and separating the space into compartments. The dividing wall has a lower end fixed to the principal surface and includes, on a sidewall, a terrace positioned further away from the principal surface than the lower end and hanging out toward the space compared to the lower end in a second direction parallel to the principal surface and perpendicular to the first direction. A terminal's bonding part, to which a wire is bonded, is disposed on the terrace. A ratio of the wire's diameter to the bonding part's width in the first direction is set to ?0.15, which prevents a situation where bonding power is not sufficiently applied to the bonding part during ultrasonic bonding of the wire, thus increasing the bonding strength.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 29, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki KANAI, Shun OKADA, Ryoichi KATO
  • Patent number: 11437302
    Abstract: Provided are a semiconductor module capable of easily connecting extraction pin with a wiring board and having reliable connections, and a method for manufacturing the same. A semiconductor module includes: a multilayer board having a semiconductor device mounted thereon, the multilayer board electrically connecting to the semiconductor device; an extraction pin electrically connecting to one of the semiconductor device and the multilayer board; and a wiring board bonded to the extraction pin for electrical connection. The extraction pin has a press-fit. The wiring board has a hole portion bonded with the press-fit of the extraction pin. The base materials of the press-fit of the extraction pin and the hole portion of the wiring board are copper (Cu). A bonded portion between the base materials of press-fit and the corresponding hole portion of the wiring board includes a CuSnNi alloy layer.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 6, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Kanai, Yuichiro Hinata
  • Publication number: 20220278018
    Abstract: A semiconductor device includes a semiconductor chip, an insulated circuit board including a metal plate, an insulating plate and a circuit pattern, each of which has a rectangular shape, and a spacer part disposed on the periphery of a rear surface of the metal plate including at least one of the four corners thereof. The spacer part protrudes from a rear surface of the metal plate in the thickness direction away from a front surface of the insulated circuit board.
    Type: Application
    Filed: January 27, 2022
    Publication date: September 1, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yushi SATO, Yuichiro HINATA, Naoyuki KANAI
  • Patent number: 11398450
    Abstract: A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Patent number: 11398448
    Abstract: A semiconductor module includes first to fourth semiconductor elements, each having an upper-surface electrode and a lower-surface electrode, first to fourth conductive layers, each extending in a first direction and being independently disposed side by side in a second direction orthogonal to the first direction, and an output terminal connected to the second and third conductive layers. The lower-surface electrodes of each of the first to fourth semiconductor elements are respectively conductively connected to the first to fourth conductive layers. The third conductive layer and the fourth conductive layer are disposed between the first conductive layer and the second conductive layer and are connected to the output terminal to have an equal potential.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Publication number: 20220208652
    Abstract: A semiconductor module includes a resin case housing a semiconductor element; an insulating layer extending outward from the resin case; and a first external connection terminal extending outward from the resin case, arranged above the insulating layer so as to face the insulting layer, the first external connection terminal having a non-contact portion that is not in contact with the insulating layer in a thickness direction of the insulating layer at a position overlapping the insulating layer in a plan view.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 30, 2022
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Yuichiro HINATA, Yuma MURATA, Naoyuki KANAI, Ryoichi KATO
  • Patent number: 11335660
    Abstract: A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Patent number: 11309276
    Abstract: A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuma Murata, Ryoichi Kato, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Publication number: 20220068733
    Abstract: A semiconductor module is provided with: a case having a frame that surrounds a substrate and a terminal block formed extending inward from an inner wall surface of the frame; a terminal having one end extending outward from the frame, and another end extending inward from the frame and being secured to a top face of the terminal block; a wiring member that electrically connects the terminal and a semiconductor element on the substrate; and an encapsulating resin that encapsulates the other end of the terminal, the wiring member, and the semiconductor element inside the case. A hole is formed in the top face of the terminal block. The hole is filled with the encapsulating resin, and is positioned closer to the inner wall surface of the frame than a bonding part between the terminal and the wiring member.
    Type: Application
    Filed: June 30, 2021
    Publication date: March 3, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki KANAI, Yuichiro HINATA, Yuta TAMAI
  • Publication number: 20210398880
    Abstract: Provided are a semiconductor module capable of easily connecting extraction pin with a wiring board and having reliable connections, and a method for manufacturing the same. A semiconductor module includes: a multilayer board having a semiconductor device mounted thereon, the multilayer board electrically connecting to the semiconductor device; an extraction pin electrically connecting to one of the semiconductor device and the multilayer board; and a wiring board bonded to the extraction pin for electrical connection. The extraction pin has a press-fit. The wiring board has a hole portion bonded with the press-fit of the extraction pin. The base materials of the press-fit of the extraction pin and the hole portion of the wiring board are copper (Cu). A bonded portion between the base materials of press-fit and the corresponding hole portion of the wiring board includes a CuSnNi alloy layer.
    Type: Application
    Filed: April 28, 2021
    Publication date: December 23, 2021
    Inventors: Naoyuki KANAI, Yuichiro HINATA
  • Patent number: 11189579
    Abstract: A semiconductor module internally includes semiconductor elements and multilayer substrates on which the semiconductor elements are arranged. The semiconductor module further includes, in a case, fastening portions for fastening a cooler such as conductive radiating fins or water-cooling jackets, for example. In the semiconductor module, side faces of heat radiating plates formed on the rear surface sides of the multilayer substrates are electrically connected to the fastening portions in the case by conductive connectors.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Satoshi Kaneko, Naoyuki Kanai
  • Publication number: 20210280550
    Abstract: A semiconductor module includes first to fourth semiconductor elements, each having an upper-surface electrode and a lower-surface electrode, first to fourth conductive layers, each extending in a first direction and being independently disposed side by side in a second direction orthogonal to the first direction, and an output terminal connected to the second and third conductive layers. The lower-surface electrodes of each of the first to fourth semiconductor elements are respectively conductively connected to the first to fourth conductive layers. The third conductive layer and the fourth conductive layer are disposed between the first conductive layer and the second conductive layer and are connected to the output terminal to have an equal potential.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 9, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yuma MURATA, Naoyuki KANAI, Akito NAKAGOME, Yoshinari IKEDA
  • Publication number: 20210280556
    Abstract: A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 9, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yuma MURATA, Naoyuki KANAI, Akito NAKAGOME, Yoshinari IKEDA