Patents by Inventor Naoyuki Komuta

Naoyuki Komuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200185373
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10217676
    Abstract: A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Naoyuki Komuta, Hiroshi Watabe
  • Patent number: 10090273
    Abstract: A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoyuki Komuta
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Patent number: 9960143
    Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Naoyuki Komuta
  • Publication number: 20180076187
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 15, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Publication number: 20170263585
    Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.
    Type: Application
    Filed: September 1, 2016
    Publication date: September 14, 2017
    Inventors: Soichi HOMMA, Naoyuki KOMUTA
  • Publication number: 20170069551
    Abstract: A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 9, 2017
    Inventors: Shinya FUKAYAMA, Naoyuki KOMUTA, Hiroshi WATABE
  • Patent number: 9449949
    Abstract: A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 20, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoyuki Komuta
  • Publication number: 20160079200
    Abstract: A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventor: Naoyuki KOMUTA
  • Patent number: 9224713
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Hiroshi Watabe, Keita Mizoguchi, Naoyuki Komuta
  • Publication number: 20150262847
    Abstract: A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventor: Naoyuki KOMUTA
  • Publication number: 20150214193
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 9052187
    Abstract: An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoyuki Komuta, Masatoshi Fukuda
  • Patent number: 9024424
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Publication number: 20140206144
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi TSUKIYAMA, Masatoshi FUKUDA, Hiroshi WATABE, Keita MIZOGUCHI, Naoyuki KOMUTA
  • Patent number: 8710654
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Hiroshi Watabe, Keita Mizoguchi, Naoyuki Komuta