Abstract: A control circuit for digital data transfer between two digital circuits provided with two different bus architectures. The circuit includes two data bus transceivers which are controlled in a manner which determines data transfer between two CPU packages which are rendered compatible. The data bus transceivers are further controlled such that only one data bus transceiver is selectively rendered operative. The two data bus transceivers are respectively assigned to two memory units. One of the memory units is made active in the event that the data bus transceiver assigned thereto is rendered operative, while the other memory unit is made active in the event that the other data bus transceiver assigned thereto is rendered operative.