Patents by Inventor Naoyuki Miyazawa
Naoyuki Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12119311Abstract: Provided is an amplifier device including a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The package includes a metal base, an insulating side wall, an input lead, and an output lead. The input lead is connected to a gate pad group of the semiconductor chip. The output lead is connected to a drain pad group of the semiconductor chip. Each of the feedback circuits includes a dielectric substrate disposed on the metal base, a feedback resistor located on the dielectric substrate, and a capacitor connected in series to the feedback resistor. Each of the feedback circuits is connected between the gate pad group and the drain pad group. The feedback circuits are located respectively on the base on one side and the other side of the semiconductor chip in an extension direction of a first and a second end edge.Type: GrantFiled: May 25, 2020Date of Patent: October 15, 2024Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Patent number: 11588441Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1D and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.Type: GrantFiled: December 17, 2020Date of Patent: February 21, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Patent number: 11533026Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.Type: GrantFiled: July 28, 2020Date of Patent: December 20, 2022Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki Miyazawa
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Publication number: 20220254743Abstract: Provided is an amplifier device including a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The package includes a metal base, an insulating side wall, an input lead, and an output lead. The input lead is connected to a gate pad group of the semiconductor chip. The output lead is connected to a drain pad group of the semiconductor chip. Each of the feedback circuits includes a dielectric substrate disposed on the metal base, a feedback resistor located on the dielectric substrate, and a capacitor connected in series to the feedback resistor. Each of the feedback circuits is connected between the gate pad group and the drain pad group. The feedback circuits are located respectively on the base on one side and the other side of the semiconductor chip in an extension direction of a first and a second end edge.Type: ApplicationFiled: May 25, 2020Publication date: August 11, 2022Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki MIYAZAWA
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Publication number: 20210104977Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1N and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki MIYAZAWA
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Patent number: 10903795Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1D and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.Type: GrantFiled: July 10, 2019Date of Patent: January 26, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Publication number: 20200358408Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.Type: ApplicationFiled: July 28, 2020Publication date: November 12, 2020Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki MIYAZAWA
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Patent number: 10763802Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.Type: GrantFiled: October 24, 2018Date of Patent: September 1, 2020Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki Miyazawa
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Publication number: 20200021246Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal T installed on one side of a wiring substrate 3, an output terminal TIN installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1D and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.Type: ApplicationFiled: July 10, 2019Publication date: January 16, 2020Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki MIYAZAWA
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Patent number: 10396025Abstract: A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor chip, an impedance converter, a capacitor, and a bonding wire. The housing includes a heat sink, an output lead terminal, and a bias terminal electrically isolated from the output lead terminal. The semiconductor chip is mounted on the heat sink of the housing. The impedance converter provides an input port, an output port, and an intermediate port between the input port and the output port thereof. The capacitor is mounted on the heat sink and between the impedance converter and the output lead terminal. The bonding wire connects the bias lead terminal with the intermediate port.Type: GrantFiled: November 20, 2017Date of Patent: August 27, 2019Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Yuichi Hasegawa, Naoyuki Miyazawa
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Publication number: 20190123697Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for suppling an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.Type: ApplicationFiled: October 24, 2018Publication date: April 25, 2019Inventor: Naoyuki Miyazawa
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Publication number: 20180145023Abstract: A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor chip, an impedance converter, a capacitor, and a bonding wire. The housing includes a heat sink, an output lead terminal, and a bias terminal electrically isolated from the output lead terminal. The semiconductor chip is mounted on the heat sink of the housing. The impedance converter provides an input port, an output port, and an intermediate port between the input port and the output port thereof. The capacitor is mounted on the heat sink and between the impedance converter and the output lead terminal. The bonding wire connects the bias lead terminal with the intermediate port.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Yuichi HASEGAWA, Naoyuki MIYAZAWA
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Patent number: 9866186Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.Type: GrantFiled: April 15, 2016Date of Patent: January 9, 2018Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Publication number: 20160233841Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.Type: ApplicationFiled: April 15, 2016Publication date: August 11, 2016Inventor: Naoyuki Miyazawa
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Patent number: 9331640Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.Type: GrantFiled: January 23, 2015Date of Patent: May 3, 2016Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki Miyazawa
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Publication number: 20150214905Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.Type: ApplicationFiled: January 23, 2015Publication date: July 30, 2015Inventor: Naoyuki MIYAZAWA
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Patent number: 8258851Abstract: There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET.Type: GrantFiled: March 9, 2010Date of Patent: September 4, 2012Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Naoyuki Miyazawa
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Publication number: 20120075004Abstract: A switch includes, a common terminal, a first terminal, a second terminal, a first FET having a first source, a first drain and a first gate, one of the first source and the first drain being coupled to the common terminal, the other of the first source and the first drain being coupled to the first terminal, and a second FET having a second source, a second drain and a second gate, one of the second source and the second drain being coupled to the common terminal, the other of the second source and the second drain being coupled to the second terminal. The first FET is controlled to a turn-off state by an absolute voltage of the first gate which is smaller than an absolute voltage of the second gate to control a turning-off state for the second transistor.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Publication number: 20100237928Abstract: There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET.Type: ApplicationFiled: March 9, 2010Publication date: September 23, 2010Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
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Patent number: 7626443Abstract: A switching circuit includes switching transistors connected to one of an input terminal and an output terminal of the switching circuit, and a control bias supply circuit that supplies a control bias for cutting off all the switching transistors to the switching transistors when all of the switching transistors are in a non-selected state.Type: GrantFiled: February 5, 2008Date of Patent: December 1, 2009Assignee: Fujitsu Quantum Devices LimitedInventors: Takayaki Kitazawa, Naoyuki Miyazawa