Abstract: On a front surface of a semiconductor base, a first n?-type drift region and a second n-type drift region are provided. A gate trench is provided that penetrates an n+-type source region and p-type base region, and reaches the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region and the p-type base region, and reaches a p-type semiconductor region, through the second n-type drift region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at a bottom and corners of the contact trench, and forms a Schottky junction with the second n-type drift region at side walls of the contact trench. A depth of the contact trench is a depth by which a mathematical area of a part thereof forming the Schottky junction is a predetermined mathematical area or greater.

Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.

Abstract: At a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, an n++-type source region, a p-type base layer, and a trench that reaches the n?-type drift layer are provided. The silicon carbide semiconductor device has a recess provided between adjacent trenches. The recess has a side surface and a bottom surface that form an angle of 15° to 80°. A SBD part is provided at the bottom surface of the recess and forms a Schottky contact with the n?-type drift layer.

Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

Abstract: In forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic. The n+-type source region has an arsenic concentration profile and a nitrogen concentration profile formed to overlap each other at a different depth from the front surface of the base substrate. A peak of the nitrogen concentration profile is positioned deeper than a peak of the arsenic concentration profile from the front surface of the base substrate. The overall impurity concentration distribution of the n+-type source region is a concentration profile that is formed by summing the arsenic concentration profile and the nitrogen concentration profile with each other and whose diffusion depth is large.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region contains arsenic.

Abstract: Heat treatment is performed twice with respect to a silicon carbide substrate. In the first heat treatment process, after Si ions are implanted in a front surface of the silicon carbide substrate, the silicon carbide substrate contacting an electrode film is heat treated, and a precursor layer of a thermal reaction layer is formed between the electrode film and the silicon carbide substrate that includes a high-concentration impurity region. Thereafter, the unreacted electrode film remaining on the precursor layer of the thermal reaction layer and on an oxide film is removed. In the subsequent second heat treatment process, the silicon carbide substrate from which the unreacted electrode film has been removed is heat treated and the precursor layer of the thermal reaction layer at a bottom area of the opening is converted into the thermal reaction layer.

Abstract: Heat treatment is performed twice with respect to a silicon carbide substrate. In the first heat treatment process, after Si ions are implanted in a front surface of the silicon carbide substrate, the silicon carbide substrate contacting an electrode film is heat treated, and a precursor layer of a thermal reaction layer is formed between the electrode film and the silicon carbide substrate that includes a high-concentration impurity region. Thereafter, the unreacted electrode film remaining on the precursor layer of the thermal reaction layer and on an oxide film is removed. In the subsequent second heat treatment process, the silicon carbide substrate from which the unreacted electrode film has been removed is heat treated and the precursor layer of the thermal reaction layer at a bottom area of the opening is converted into the thermal reaction layer.

Abstract: An interlayer insulating film is patterned, contact holes are formed, and in the contact holes, a source contact portion forming an ohmic contact with the silicon carbide body is formed. Thereafter, a titanium film and an aluminum wiring layer are continuously formed in this sequence on the interlayer insulating film and the source contact portion. At this time, the thickness of the titanium film is about 1.0 ?m or less. Thereafter, by heat treatment for curing of a passivation film or heat treatment thereafter, the titanium film and the aluminum wiring layer react, generating a TiAl alloy film between the titanium film and the aluminum wiring layer. The thickness of the TiAl alloy film, for example, is kept to about 1 nm to 100 nm; and the TiAl alloy film and the source contact portion do not contact each other.

Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.

Abstract: A photovoltaic cell includes a photoelectric conversion element (PCE) in which an i-type silicon layer formed of a microcrystalline silicon film is provided between an n-type silicon layer and a p-type silicon layer, and the n-type silicon layer or p-type silicon layer positioned on a substrate side is configured of an amorphous silicon film. The PCE is formed wherein a mixture of a silane containing gas and hydrogen gas is introduced into a chamber and a seed layer formed of a microcrystalline silicon film is formed between the n-type silicon layer or p-type silicon layer positioned on the substrate side and the i-type silicon layer. The crystallization rate of a portion in contact with the n-type silicon layer or p-type silicon layer positioned on the substrate side is lower than that of the i-type silicon layer, and the rate increases continuously, or gradually in two or more stages, toward the i-type silicon layer side, continuing to the i-type silicon layer.